adm6993 Infineon Technologies Corporation, adm6993 Datasheet - Page 35

• Manufacturer Part Number: adm6993
• Description: Adm6993/x Hdlc To Fast Ethernet Converter
• Manufacturer: Infineon Technologies Corporation

Table 19
Register Short Name
TPR_0_0
TPR_1_0
TPR_0_1
TPR_1_1
TPR_0_2
TPR_1_2
TPR_0_3
TPR_1_3
TPR_0_4
TPR_1_4
TPR_0_5
TPR_1_5
TPR_0_6
TPR_1_6
TPR_0_7
TPR_1_7
MCR_3
MCR_4
MCR_5
MCR_6
The register is addressed wordwise.
Table 20
Mode
read/write
read
Read only
Read virtual
Latch high,
self clearing
Latch low,
self clearing
Latch high,
mask clearing
Latch low,
mask clearing
Data Sheet
Registers Overview (cont’d)
Register Access Types
Symbol Description HW
rw
r
ro
rv
lhsc
llsc
lhmk
llmk
Register Long Name
Tag Port Rule 0 Register 0
Tag Port Rule 1 Register 0
Tag Port Rule 0 Register 1
Tag Port Rule 1 Register 1
Tag Port Rule 0 Register 2
Tag Port Rule 1 Register 2
Tag Port Rule 0 Register 3
Tag Port Rule 1 Register 3
Tag Port Rule 0 Register 4
Tag Port Rule 1 Register 4
Tag Port Rule 0 Register 5
Tag Port Rule 1 Register 5
Tag Port Rule 0 Register 6
Tag Port Rule 1 Register 6
Tag Port Rule 0 Register 7
Tag Port Rule 1 Register 7
Miscellaneous Configuration Register 3
Miscellaneous Configuration 4
Miscellaneous Configuration Register 5
Miscellaneous Configuration Register 6
Register is used as input for the HW
Register is written by HW (register
between input and output -> one cycle
delay)
Register is set by HW (register between
input and output -> one cycle delay)
Physically, there is no new register, the
input of the signal is connected directly
to the address multiplexer.
Latch high signal at high level, clear on
read
Latch high signal at low-level, clear on
read
Latch high signal at high level, register
cleared with written mask
Latch high signal at low-level, register
cleared on read
35
Description SW
Register is read and writable by SW
Value written by software is ignored by
hardware; that is, software may write any
value to this field without affecting hardware
behavior (= Target for development.)
SW can only read this register
SW can only read this register
SW can read the register
SW can read the register
SW can read the register, with write mask
the register can be cleared (1 clears)
SW can read the register, with write mask
the register can be cleared (1 clears)
Offset Address
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Registers Description
Rev 1.11, 2005-11-28
Page Number
51
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52
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52
51
52
51
52
51
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54
54
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ADM6993/X