qf4a512 ETC-unknow, qf4a512 Datasheet - Page 20

• Manufacturer Part Number: qf4a512
• Description: 4-channel Programmable Signal Converter Psc
• Manufacturer: ETC-unknow

PRELIMINARY
QF4A512
7.3 Aggregate Bandwidth
The aggregate bandwidth is the total bandwidth available to all active channels. If only one channel is active then it can use the entire
bandwidth, but as further channels are activated the bandwidth available to each will be reduced. Since the oversampling rate can be
adjusted for each channel the bandwidth for that channel should be calculated based on its own effective sampling rate. Although
Nyquist suggests the sampling rate should be twice the highest frequency of interest it is recommended that a factor of 2.2 be used for
optimum performance.
7.4 Serial Interface
For higher frequencies of interest the data rate across the SPI bus must also be considered. The maximum clock rate for the bus is
40MHz which results in a maximum 1.66MHz word rate for 24-bit transfers (multi-channel mode), or 2.5MHz word rate for 16-bit
transfers (single channel mode). Allowing for further bandwidth reductions when multiple channels are active, and by applying the 2.2
oversampling factor the maximum analog bandwidth can be determined as shown in the table.
Table 2. Maximum Analog Input Frequency @40MHz SPI bus clock
Single Channel
Multi-channel Mode
Mode
1 channel
2 channels
3 channels
4 channels
Maximum analog input
1.136MHz
757kHz
378.8kHz
252kHz
189kHz
frequency
Maximum sampling rate
2.5Msps
1.6Msps
800ksps
533ksps
400ksps
7.5 Data Format
The filtered ADC output words are always 16 bits in length. (The 24-bit words output in multi-channel mode comprise a 16-bit data word
plus channel ID and status info, see section 10, Serial Interface). The output format is 2’s complement so the msb can be regarded as a
sign bit. The maximum positive value is 7FFFh, corresponding to an input differential voltage of +1V. The most negative value is 8000h,
corresponding to an input differential voltage of -1V (assuming 1x gain).
Each lsb will correspond to 30.5μV at the input with a PGA gain of 1, 15.25μV with a gain of 2, 7.63μV with a gain of 4 and 3.81μV with
a gain of 8.
7.6 Analog Mux
The ADC samples each input channel in turn at the output of the analog multiplexer. It takes 9 clock cycles to complete each sample so
there is a latency of 9N clock cycles before a complete sample is passed on to the next stage (where N is the number of active
channels). Thereafter the pipeline architecture of the ADC will output data on every cycle for subsequent samples. The data samples
from the ADC are accumulated and decimated in the CIC/CIH blocks for each respective channel.
Minimum crosstalk is achieved at ADC clock rates of 50MHz or less. Operation at rates up 100MHz is possible for single-channel
operation or when some degradation in crosstalk is permissible.
7.7 Gain and Offset Calibration
Provision is provided on chip to calibrate both gain and offset to compensate for deviations from nominal performance in the Analog
Front End and ADC. The calibration registers can also be user configured to compensate for variations in external components in the
user’s application circuit.
Offset calibration, on a per channel basis, is achieved by use of the CAL_n_OFF register (addresses 56h, 57h for channel 1). This 16-
bit value has a default setting of 0h. By appropriately setting this register, offset error can be reduced to less than 1 lsb, well below the
noise floor of the device. Typically this register is set to produce a zero output with the input shorted to ground.
Note: If the chopper circuit is used the offset error is effectively removed with no need for calibration.
Gain calibration can be used to fine tune the gain of the chip over a 2:1 range. Register CAL_n_GAIN (addresses 58h, 59h for channel
1) is used to set the gain on a per channel basis. The nominal / default value for this 16-bit value is 8000h, increasing or decreasing the
value will adjust the gain in either direction. User gain calibration can be performed by applying a specific voltage to the analog input
and adjusting the value of the CAL_n_GAIN registers until the appropriate output value is achieved. When used in conjunction with the
PGA gain setting it is equivalent to having the ability to scale the input voltage over approximately a 0.5x to 16x range in fine
increments.
Rev C5, Jan 07
20
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