qf4a512 ETC-unknow, qf4a512 Datasheet - Page 7

• Manufacturer Part Number: qf4a512
• Description: 4-channel Programmable Signal Converter Psc
• Manufacturer: ETC-unknow

†
5V levels.
Note: Current device revision is QF4A512A. Only difference between this revision and previous revisions is a reduction in standby
1.5 Timing Requirements
Parameter
Input Clock Frequency, f
Serial Port Clock Frequency, f
Serial Port Clock Frequency, f
PLL Clock Frequency, PLL_CLK
Chip select low pulse width
SYS_CLK frequency (User filters, sampling rates)
SYS_CLK frequency (Fixed G and H filters)
SYS_CLK frequency (relative to SCLK)
Setup time, Chip Select (/CS) low to SCLK
Setup time, SDI before SCLK
Hold time, SDI after SCLK
Rev C5, Jan 07
The digital input and output pins (except XIN & XOUT) are 5V-tolerant. Inputs may be driven with 5V signals, outputs can be connected via pull-ups to
V
V
C
C
OH
OL
O
L
1. System calibration will reduce these errors to below the noise level.
2. System calibration at any temperature will eliminate this error.
3. Programmable Gain Amplifier set at a gain of x1, f
4. Standby is with all channels inactive, and analog front end turned off. Power down is when the oscillator/PLL is turned off.
5. f
6. This parameter is derived in similar fashion to the previous one and is determined by the fixed number
7. This limit is caused by the requirement for DRDY to be cleared before /CS returns to a high level after
8. All three of the minimum conditions must be satisfied for correct device operation.
power (P
FIR. The highest value of the expression for any active channel defines the minimum frequency for
SYS_CLK.
of taps used in the G and H filters.
a data transfer. Two SYS_CLKS are required to clear DRDY this must occur before the data transfer is
completed. N is the number of channels active in the output data.
S
High-level Output Voltage, DV
Low-level Output Voltage, DV
Output Capacitance
Load Capacitance
is the sampling rate for any given channel and N
DD
) and correct implementation of the ADC overflow flags (Section 10.3)
0
↑
↑
EE
SCLK
(EEPROM Mode)
(Run and Configure Modes)
DD18
DD18
- 16-bit output
- 24-bit output
↑
= 2.0V, I
= 1.6V, I
OL
OH
= 100uA
= -100uA
IN
= f
TAPS
s
/ 25
PRELIMINARY
is the number of taps used in the associated
(((N
7
TAPS
2/SYS_CLK
SCLK/(8*N)
3*SCLK/16
103* f
+ 1)/2)+1)*f
Min
tbd
tbd
tbd
20
5
1.4
S
tbd
S
PLL_CLK
PLL_CLK
PLL_CLK
Max
0.2
100
200
20
40
5
pF
pF
V
V
Units
MHz
MHz
MHz
MHz
ns
ns
ns
ns
Note
5, 8
6, 8
7, 8
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QF4A512