px1041a NXP Semiconductors, px1041a Datasheet

px1041a

Manufacturer Part Number

px1041a

Description

Pci Express Stand-alone X4 Phy Semiconductors

Manufacturer

NXP Semiconductors

Datasheet

1.PX1041A.pdf (36 pages)

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1. General description

2. Features

2.1 PCI Express interface

2.2 PHY/MAC interface

The PX1041A is a high-performance, low-power, four-lane PCI Express electrical

PHYsical layer (PHY) that handles the low level PCI Express protocol and signaling. The

PX1041A PCI Express PHY is compliant to the PCI Express Base Speciﬁcation,

Rev. 1.0a , and Rev. 1.1 . The PX1041A includes features such as Clock and Data

Recovery (CDR), data serialization and de-serialization, 8b/10b encoding, analog buffers,

elastic buffer and receiver detection, and provides superior performance to the Media

Access Control (MAC) layer devices.

The PX1041A is a 2.5 Gbit/s PCI Express PHY with 4

PXPIPE interface is a superset of the PHY Interface for the PCI Express (PIPE)

speciﬁcation, enhanced and adapted for off-chip applications with the introduction of a

source synchronous clock for transmit and receive data. The 4

operates at 250 MHz with SSTL Class I signaling at 2.5 V or 1.8 V. The SSTL signaling is

compatible with the I/O interfaces available in FPGA products.

The PX1041A PCI Express PHY supports advanced power management functions. The

PX1041AI is for the industrial temperature range ( 40 C to +85 C).

PX1041A

PCI Express stand-alone X4 PHY

Rev. 01 — 21 June 2007

Compliant to PCI Express Base Speciﬁcation 1.0a and 1.1

Four PCI Express 2.5 Gbit/s lane

Data and clock recovery from serial stream

Serializer and De-serializer (SerDes)

Receiver detection

8b/10b coding and decoding, elastic buffer and word alignment

Supports direct disparity control for use in transmitting compliance pattern

Supports lane polarity inversion

Low jitter and Bit Error Rate (BER)

Supports PCI Express-side parallel loopback

Supports PXPIPE-side parallel loopback

Supports receiver lane-to-lane deskew (optional)

Supports lane reversal (optional)

Based on Intel PHY Interface for PCI Express architecture v2.0 (PIPE)

Adapted for off-chip with additional synchronous clock signals (PXPIPE)

8-bit data PXPIPE interface. Its

8-bit data interface

Objective data sheet

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