px1041a NXP Semiconductors, px1041a Datasheet - Page 27

• Manufacturer Part Number: px1041a
• Description: Pci Express Stand-alone X4 Phy Semiconductors
• Manufacturer: NXP Semiconductors

NXP Semiconductors
11. Characteristics
Table 20.
PX1041A_1
Objective data sheet
Symbol
Supplies
V
V
V
V
V
V
V
I
I
I
I
I
I
Reference clock
f
f
V
V
Receiver
UI
V
t
V
Z
Z
RL
RL
t
t
t
L
DDD1
DDD2
DDD3
DD
DDA1
DDA2
clk(ref)
mod(clk)(ref)
RX_MAX_JITTER
lock(CDR)(ref)
lock(CDR)(data)
RX_latency
RX_SKEW
DDD1
DDD2
DDD2
DDD3
DD
DDA1
DDA2
f
IH(se)REFCLK
IL(se)REFCLK
RX_DIFFp-p
IDLE_DET_DIFFp-p
RX_DC
RX_HIGH_IMP_DC
mod(clk)(ref)
RX_DIFF
RX_CM
PCI Express PHY characteristics
Parameter
digital supply voltage 1
digital supply voltage 2
digital supply voltage 2
digital supply voltage 3
supply voltage
analog supply voltage 1
analog supply voltage 2
digital supply current 1
digital supply current 2
digital supply current 3
supply current
analog supply current 1
analog supply current 2
reference clock frequency
reference clock SSC modulation
frequency deviation
reference clock SSC modulation
frequency
REFCLK single-end HIGH-level input
voltage
REFCLK single-end LOW-level input
voltage
unit interval
differential input peak-to-peak voltage
maximum receiver jitter time
electrical idle detect threshold
DC input impedance
powered-down DC input impedance
differential return loss
common mode return loss
CDR lock time (reference loop)
CDR lock time (data loop)
receiver latency
total skew
Rev. 01 — 21 June 2007
Conditions
for JTAG I/O
for SSTL_18 I/O
for SSTL_2 I/O
for core
for high-speed
serial I/O and PVT
for serializer
for serializer
for JTAG I/O
for SSTL I/O;
no load
for core
for high-speed
serial I/O and PVT
for serializer
for serializer
1 clock cycle is
4 ns
PCI Express stand-alone X4 PHY
Min
3.0
1.7
2.3
1.15
1.15
1.15
3.0
-
-
-
-
-
-
99.97
30
-
-
399.88 400
0.175
-
65
40
200
10
6
-
-
-
-
0.5
Typ
3.3
1.8
2.5
1.2
1.2
1.2
3.3
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
100
-
-
0.7
0
-
-
-
50
-
-
-
<tbd>
<tbd>
<tbd>
-
PX1041A
© NXP B.V. 2007. All rights reserved.
Max
3.6
1.9
2.7
1.25
1.25
1.25
3.6
2
80
60
100
100
60
100.03 MHz
+0
33
-
-
400.12 ps
1.2
0.6
175
60
-
-
-
-
-
-
20
Unit
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
%
kHz
V
V
V
UI
mV
k
dB
dB
clock
cycle
ns
27 of 36
s
s