mk5025q-1002 STMicroelectronics, mk5025q-1002 Datasheet

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mk5025q-1002

Manufacturer Part Number

mk5025q-1002

Description

High Speed Link Level Controller

Manufacturer

STMicroelectronics

Datasheet

1.MK5025Q-1002.pdf (64 pages)

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SECTION 1 - FEATURES

July 1994

System clock rate up to 33 MHz (MK50H25 -

33), 25 MHz (MK50H25 - 25), or 16 MHz

(MK50H25 - 16).

Data

(MK50H25 - 33) or up to 51 Mbps bursted

On chip DMA control with programmable burst

length.

DMA transfer rate of up to 13.3 Mbytes/sec us-

ing optional 5 SYSCLK DMA cycle (150 nS) at

33 MHz SYSCLK.

Complete Level 2 implementation compatible

with X.25 LAPB, ISDN LAPD, X.32, and X.75

Protocols.

Handles all error recovery, sequencing, and S

and U frame control.

Pin-for-pin and architecturally compatible with

MK5025 (X.25/LAPD), MK5027 (CCS#7) and

MK5029(SDLC).

Buffer Management includes:

Separate 64-byte Transmit and Receive FIFO.

Programmable Transmit FIFO hold-off water-

mark.

Handles all HDLC frame formatting:

Programmable Single or Extended Address

and Control fields.

Five programmable timer/counters:

TP, N1, N2

Programmable minimum frame spacing on

transmission

frames).

- Programmable from 1 to 62 flags between

frames

Selectable FCS (CRC) of 16 or 32 bits, and

passing of entire FCS to buffer.

Testing Facilities:

Programmable for full or half duplex operation

- Initialization Block

- Separate Receive and Transmit Rings

- Variable Descriptor Ring and Window Sizes.

- Zero bit insertion and deletion

- FCS (CRC) generation and detection

- Frame delimiting with flags

- Internal Loopback

- Silent Loopback

- Optional Internal Data Clock Generation

- Self Test.

rate

up

(number

to

20

of

Mbps continuous

flags

between

T1, T3,

SECTION 2 - INTRODUCTION

The SGS - Thomson MK502H5 Link Level Con-

troller is a VLSI semiconductor device which pro-

vides complete link level data communications

control conforming to the 1984 and 1988 CCITT

versions of X.25. The MK50H25 will perform

frame formating including: frame delimiting with

flags, transparency (so-called ”bit-stuffing”), error

recovery by retransmission, sequence number

control, S (supervisory) and U (unnumbered)

frame control, plus FCS (CRC) generation and

detection. The MK50H25 also supports X.75 and

X.32 (with its XID frame support), as well as sin-

gle channel ISDN LAPD (with its support of UI

frames and extended addressing capabilities).

and TCLK (to detect absence of data clocks)

odd-byte aligned, in addition to standard even-

byte alignment.

with external ROM), or 48 pin DIP packages.

Programmable Watchdog Timers for RCLK

Option causing received data to effectively be

Available in 52 pin PLCC, 84 pin PLCC(for use

LINK LEVEL CONTROLLER

PLCC 52

DIP48

HIGH SPEED

MK50H25

ADVANCE DATA

1/64

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