mk5025q-1002 STMicroelectronics, mk5025q-1002 Datasheet - Page 55

• Manufacturer Part Number: mk5025q-1002
• Description: High Speed Link Level Controller
• Manufacturer: STMicroelectronics

MK50H25
Figure 8a: MK50H25 Reduced Cycle BUS Master Timing (Write) (for CYCLE = 1, CSR2<15>)
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DAL0-15
A 16-23
SYSCLK
READY
BM0,1
DALO
HOLD
HLDA
READ
DALI
DAS
ALE
NOTES:
1. This Reduced DMA Cycle Time is selected by setting CSR2 bit 15, CYCLE = 1.
2. Output delay times are the maximum delay from the specifed edge to a valid output.
3. The Bus Master cycle time will increase from a minimum, in 1 SYSCLK increments
Times T0 and T5 from the standard DMA Cycle are removed for this reduced timing.
until the slave device returns READY.
24
45
27
23
23
64
29
T 1
25
ADDR
33
T 2
43
40
T 3
ADDRESS
60
34
T 4
44
DATA
T 5
28
61
26
41
65
42
22
48
35
48