lm4934rlx National Semiconductor Corporation, lm4934rlx Datasheet
lm4934rlx
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lm4934rlx Summary of contents
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... I2C/SPI compatible interface for control. Boomer audio power amplifiers are designed specifically to provide high quality output power with a minimal amount of external components. Boomer ® registered trademark of National Semiconductor Corporation. © 2006 National Semiconductor Corporation Key Specifications Stereo BTL, 8Ω, 3.3V, ...
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Block Diagram FIGURE 1. Audio Sub-System Block Diagram with OCL HP Outputs www.national.com FIGURE 2. Audio Sub-System with SE HP Outputs 2 20166949 201669J7 ...
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Connection Diagrams Pin Descriptions PIN PIN NAME D/A A1 DGND D A2 MCLK D A3 I2S_WS D A4 GPIO D A5 ADDR/ENB D A6 DVDD D B1 PLLVDD D B2 I2S_SDI D B3 I2S_CLK D B4 MODE D B5 I2C_VDD ...
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Pin Descriptions (Continued) D1 AGND BYPASS A D5 LINEOUT A D6 RHP R3DOUT A E5 LHP A E6 ...
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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Analog Supply Voltage Digital Supply Voltage Storage Temperature Input Voltage Power Dissipation (Note 3) ESD Susceptibility (Note 4) ESD ...
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Audio Amplifier Electrical Characteristics AV 2) (Continued) The following specifications apply for the circuit shown in Figure 1 with all programmable gain set at 0dB, unless otherwise specified. Limits apply for T = 25˚C. A Symbol Parameter Xtalk Crosstalk T ...
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Audio Amplifier Electrical Characteristics AV 2) (Continued) The following specifications apply for the circuit shown in Figure 1 with all programmable gain set at 0dB, unless otherwise specified. Limits apply for T = 25˚C. A Symbol Parameter PSRR Power Supply ...
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Digital Section Electrical Characteristics The following specifications apply for 3V ≤ 25˚C. Symbol Parameter DI Digital Shutdown Current SD DI Digital Power Supply Current DD PLLI PLL Quiescent Current DD Audio DAC (Typical numbers are with 6.144MHz audio ...
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Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications ...
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Dynamic Range and SNR. 3V ≤ www.national.com TABLE 4. Dynamic Range and SNR (Continued) ≤ 5V. All programmable gain set to 0dB. Units in dB (Typ) SNR (Typ Units dB ...
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System Control The LM4934 is controlled via either a three wire SPI or a two wire I 2 MODE is cleared the device mode, when MODE is set the device is in SPI mode. This interface ...
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System Control (Continued) 2 When the part is configured device then the LM4934 will respond to one of two addresses, according to the ADDR input. If ADDR is low then the address portion of the I ...
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System Controls TABLE 7. Stereo or Mono, Left or Right Volume Control MONO_VOL_4, MONO_VOL_3, LS_L_VOL_4, LS_L_VOL_3, LS_R_VOL_4, LS_R_VOL_3, HP_L_VOL_4, HP_L_VOL_3, HP_R_VOL_4 HP_R_VOL_3 ...
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System Controls (Continued) Mode CD3 CD2 CD1 ...
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System Controls (Continued) Loudspeaker Left Channel Loudspeaker Right Channel Headphone Left Channel Headphone Right Channel Mono Speaker Output Lineout Headphone Output Mode Headphone Output set to Capless All Outputs Outputs Toggled Via Register Control TABLE 10. National 3D Enhancement Level ...
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System Controls (Continued) MONO_IN_GAIN_2 ANA_L_GAIN_2 ANA_R_GAIN_2 DIG_L_GAIN_1 DIG_R_GAIN_1 PLL Configuration Registers PLL M DIVIDER CONFIGURATION REGISTER This register is used to control the input divider of the PLL. ...
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PLL Configuration Registers PLL N DIVIDER CONFIGURATION REGISTER This register is used to control PLL N divider. PLL_N (0Bh) (Set = logic 1, Clear = logic 0) Bits 7:0 NOTES: The divider should be set such that the output of ...
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PLL Configuration Registers PLL N MODULATOR AND DITHER SELECT CONFIGURATION REGISTER This register is used to control the Fractional component of the PLL. PLL_N_MOD (0Ch) (Set = logic 1, Clear = logic 0) Bits Register 4:0 PLL_N_MOD 6:5 DITHER_LEVEL 7 ...
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Further Notes on PLL Programming The sigma-delta PLL is designed to drive audio circuits requiring accurate clock frequencies 25MHz with frequency errors noise-shaped away from the audio band. The 5 bits of modulus control provide exact synchronization ...
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Further Notes on PLL Programming Choose a small range that the VCO frequency is swept between 45 and 55MHz (or 60-80MHz if VCOFAST is used). Remembering that the P divider can divide by half integers. So for ...
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Clock Configuration Register By default the stereo DAC operates at 250*fs, i.e. 12.000MHz (at the clock generator input clock) for 48kHz data expected that the PLL be used to drive the audio system unless a 12.000MHz master clock ...
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Common Clock Settings for the DAC Fs (kHz) DAC Oversampling Ratio 44.1 44 88.2 96 176.4 192 Methods for producing these clock frequencies are described in the PLL section. The R divider can be used when the master ...
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Interface Control Register This register is used to control the I2S and I INTERFACE (0Fh) (Set = logic 1, Clear = logic 0) Bits NOTES: The master I2S format depends on the DAC mode. In USB ...
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Interface Control Register FIR Compensation Filter Configuration Registers These registers are used to configure the DAC’s FIR com- pensation filter. Three 16 bit coefficients are required and must be programmed via the I2C/SPI Interface in bytes as follows: COMP_COEFF (10h ...
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Typical Performance Characteristics THD+N vs Frequency 3V Lineout 10kΩ THD+N vs Frequency 3V HP Out 16Ω THD+N vs Frequency 5V EP 32Ω 40mW ...
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Typical Performance Characteristics THD+N vs Frequency 5V HP Out 32Ω THD+N vs Output Power 3V EP Out 16Ω 1kHz L THD+N vs Output Power 3V HP Out 16Ω ...
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Typical Performance Characteristics THD+N vs Output Power 3V LS Out 8Ω 1kHz L THD+N vs Output Power 5V EP Out 32Ω 1kHz L THD+N vs Output Power 5V HP Out ...
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Typical Performance Characteristics THD+N vs I2S Level EP Out THD+N vs I2S Level Line Out PSRR vs Frequency 3V EP Out Mode 1 www.national.com (Continued) THD+N vs I2S Level 201669B1 THD+N vs I2S Level 201669B3 PSRR vs Frequency 3V EP ...
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Typical Performance Characteristics PSRR vs Frequency 3V HP Out Mode 2 PSRR vs Frequency 3V Line Out Mode 1 PSRR vs Frequency 3V LS Out Mode 2 (Continued) PSRR vs Frequency 3V HP Out Mode 4 20166906 PSRR vs Frequency ...
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Typical Performance Characteristics PSRR vs Frequency 5V HP Out Mode 2 PSRR vs Frequency 5V Line Out Mode 1 PSRR vs Frequency 5V LS Out Mode 4 www.national.com (Continued) PSRR vs Frequency 5V HP Out Mode 4 20166913 PSRR vs ...
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Typical Performance Characteristics XTalk vs Frequency 5V HP Out Mode 32Ω Output Power vs Supply Voltage EP Out 32Ω, 1% THD+N L Output Power vs Supply Voltage LS Out 8Ω, 1% ...
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Application Information The LM4934 supports both master and slave I2S transmission at either bits per word at clock rates up to 3.072MHz (48kHz stereo, 32bit). The basic format is shown below: NATIONAL SEMICONDUCTOR 3D ...
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Application Information S12 – connects VDD_I2C to Analog VDD S17 – connects BB_VDD to USB3.3V (from USB board) S19 – connects VDD_D to USB3.3V (from USB board) S20 – connects VDD_D to SPDIF receiver chip ANALOG SUPPLY JP11 — Analog ...
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Application Information MISCELLANEOUS I2S BUS SELECT S23, S24, S26, S27 – I2S Bus select. Toggles between on-board and external I2S (whether on-board SPDIF receiver is used). All jumpers must be set the same. Jumpers on top two pins selects external ...
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Revision History Rev 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 www.national.com Date 9/22/05 Started D/S by copying LM4931 (DS201009). Did major edits. 9/27/05 Input some text/Typical/Limits on the EC 10/6/05 Added table ...
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Physical Dimensions inches (millimeters) unless otherwise noted ± 3.245 1 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice ...