lm4934rlx National Semiconductor Corporation, lm4934rlx Datasheet - Page 21

• Manufacturer Part Number: lm4934rlx
• Description: 3d Audio Sub-system With Stereo Speaker, Ocl/se Stereo Headphone, Earpiece And Mono Line Level Outputs
• Manufacturer: National Semiconductor Corporation

Further Notes on PLL Programming
The sigma-delta PLL is designed to drive audio circuits requiring accurate clock frequencies of up to 25MHz with frequency errors
noise-shaped away from the audio band. The 5 bits of modulus control provide exact synchronization of 48kHz and 44.1kHz
sample rates from any common clock source when the oversampling rate of the audio system is 125fs. In systems where 128x
oversampling must be used (for example with an isochronous I2S data stream) a clock synchronous to the sample rate should
be used as input to the PLL (typically the I2S clock). If no isochronous source is available then the PLL can be used to obtain a
clock that is accurate to within typical crystal tolerances of the real sample rate.
Example Of Pll Settings For 48Khz Sample Rates
Example Pll Settings For 44.1Khz Sample Rates
These tables cover the most common applications, obtaining clocks for sample rates such as 22.05kHz and 192kHz should be
done by changing the P divider value or the R divider in the clock configuration diagram.
If the user needs to obtain a clock unrelated to those described above, the following method is advised. An example of obtaining
11.2896 from 12.000MHz is shown below.
f_in (MHz)
f_in (MHz)
11
11.2896
12
13
14.4
16.2
16.8
19.2
19.44
19.68
19.8
12.288
19.44
19.68
14.4
16.2
16.8
19.2
19.8
11
12
13
fsamp (kHz)
fsamp (kHz)
44.1
44.1
44.1
44.1
44.1
44.1
44.1
44.1
44.1
44.1
44.1
48
48
48
48
48
48
48
48
48
48
48
11
8
5
13
12
9
17
16
13.5
20.5
11
20.5
16.5
11
13
27
14
13
27
M
M
5
4
9
55.125
39.0625
22.96875
55.125
45.9375
30.625
55.78125
45.9375
38.28125
45.9375
30.625
19.53125
40.625
37.5
62.5
100
100
60
25
60
50
50
N
N
P
5
5
5
5
5
5
5
5
6
5
5
P
5
5
5
5
5
5
5
5
5
4
5
PLL_M
PLL_M
21
15
9
25
23
17
33
31
26
40
21
21
21
25
17
53
27
25
53
40
32
9
7
PLL_N
PLL_N
55
39
22
55
45
30
55
45
38
45
30
100
100
60
25
19
60
37
50
40
62
50
PLL_N_MOD
PLL_N_MOD
4
2
31
4
30
20
25
30
9
30
20
17
16
20
16
0
0
0
0
0
0
0
PLL_P
PLL_P
9
9
9
9
9
9
9
9
9
7
9
20166963
11
9
9
9
9
9
9
9
9
9
9
f_out (MHz)
f_out (MHz)
11.025000
11.025000
11.025000
11.025000
11.025000
11.025000
11.025000
11.025000
11.025000
11.025000
11.025000
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