lm4934rlx National Semiconductor Corporation, lm4934rlx Datasheet - Page 19

• Manufacturer Part Number: lm4934rlx
• Description: 3d Audio Sub-system With Stereo Speaker, Ocl/se Stereo Headphone, Earpiece And Mono Line Level Outputs
• Manufacturer: National Semiconductor Corporation

PLL Configuration Registers
PLL N DIVIDER CONFIGURATION REGISTER
This register is used to control PLL N divider.
PLL_N (0Bh) (Set = logic 1, Clear = logic 0)
NOTES:
The divider should be set such that the output of the divider is between 0.5 and 5MHz. See the PLL setup section for details. The N divider should never be set so
that (Fin/M) * N
The non-sigma-delta division of the N divider is derived from the PLL_N as such:
N = PLL_N
Fin /M is often referred to as F
PLL P DIVIDER CONFIGURATION REGISTER
This register is used to control the PLL’s P divider.
PLL_P (0Dh) (Set = logic 1, Clear = logic 0)
NOTES:
The division of the P divider is derived from PLL_P as such:
P = (PLL_P+1) / 2
Bits
3:0
>
Bits
7:0
55MHz (or 80MHz if FAST_VCO is set in the PLL_N_MOD register).
comp
(Frequency of Comparison) or F
Register
PLL_P
Register
PLL_N
(Continued)
ref
(Reference Frequency). In this document, F
19
PLL_P
Programs the PLL input divider to select:
13
14
15
...
0
1
2
3
250 → 255
1 → 10
PLL_N
Programs the PLL feedback divider:
248
249
11
12
...
0
Description
Description
comp
is used.
Divide Ratio
Divider Off
–
>
1.5
7.5
Divide Ratio
1
2
7
8
Divider Off
2.5
248
249
250
10
11
12
...
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