lm4934rlx National Semiconductor Corporation, lm4934rlx Datasheet - Page 23

• Manufacturer Part Number: lm4934rlx
• Description: 3d Audio Sub-system With Stereo Speaker, Ocl/se Stereo Headphone, Earpiece And Mono Line Level Outputs
• Manufacturer: National Semiconductor Corporation

Clock Configuration Register
By default the stereo DAC operates at 250*fs, i.e. 12.000MHz (at the clock generator input clock) for 48kHz data. It is expected
that the PLL be used to drive the audio system unless a 12.000MHz master clock is supplied. The PLL can also use the I2S clock
input as a source. In this case, the audio DAC uses the clock from the output of the PLL.
Common Clock Settings for the DAC
The DAC can work in 4 modes, each with different oversampling rates, 125,128,64 & 32. In normal operation 125x oversampling
provides for the simplest clocking solution as it will work from 12.000MHz (common in most systems with Bluetooth or USB) at
48kHz exactly. The other modes are useful if data is being provided to the DAC from an uncontrollable isochronous source (such
as a CD player, DAB, or other external digital source) rather than being decoded from memory. In this case the PLL can be used
to derive a clock for the DAC from the I2S clock.
The DAC oversampling rate can be changed to allow simpler clocking strategies, this is controlled in the DAC SETUP register but
the oversampling rates are as follows:
The following table describes the clock required at the clock generator input for various clock sample rates in the different DAC
modes:
Fs (kHz)
11.025
11.025
22.05
22.05
12
12
16
16
24
24
32
32
8
8
DAC MODE
DAC Oversampling Ratio
00
01
10
11
125
128
125
128
125
128
125
128
125
128
125
128
125
128
(Continued)
23
Required CLock at DAC Clock Generator Input (MHz)
Oversampling Ratio Used
2.75625
2.8224
5.5125
5.6448
125
128
2.048
3.072
4.096
6.144
8.192
64
32
2
3
4
6
8
20166953
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