lm5046sqx National Semiconductor Corporation, lm5046sqx Datasheet - Page 14

• Manufacturer Part Number: lm5046sqx
• Description: Phase-shifted Full-bridge Pwm Controller With Integrated Mosfet Drivers
• Manufacturer: National Semiconductor Corporation

www.national.com
PWM Comparator
The LM5046 pulse width modulator (PWM) comparator is a
three input device, it compares the signal at the RAMP pin to
the loop error signal or the soft-start, whichever is lower, to
control the duty cycle. This comparator is optimized for speed
in order to achieve minimum controllable duty cycles. The
loop error signal is received from the external feedback and
isolation circuit in the form of a control current into the COMP
pin. The COMP pin current is internally mirrored by a match-
ing pair of NPN transistors which sink current through a 5kΩ
resistor connected to the 5V reference. The resulting control
voltage passes through a 1V offset, followed by a 2:1 resistor
divider before being applied to the PWM comparator.
An opto-coupler detector can be connected between the REF
pin and the COMP pin. Because the COMP pin is controlled
by a current input, the potential difference across the opto-
coupler detector is nearly constant. The bandwidth limiting
phase delay which is normally introduced by the significant
capacitance of the opto-coupler is thereby greatly reduced.
Higher loop bandwidths can be realized since the bandwidth
limiting pole associated with the opto-coupler is now at a
much higher frequency. The PWM comparator polarity is con-
figured such that with no current flowing into the COMP pin,
the controller produces maximum duty cycle.
RAMP Pin
The voltage at the RAMP pin provides the modulation ramp
for the PWM comparator. The PWM comparator compares
the modulation ramp signal at the RAMP pin to the loop error
signal to control the duty cycle. The modulation ramp signal
can be implemented either as a ramp proportional to the input
voltage, known as feed-forward voltage mode control, or as
a ramp proportional to the primary current, known as current
mode control. The RAMP pin is reset by an internal MOSFET
with an R
The ability to configure the RAMP pin for either voltage mode
or current mode allows the controller to be implemented for
the optimum control method depending upon the design con-
DS(ON)
of 5.5Ω at the conclusion of each PWM cycle.
a) Slope Compensation Configured for PWM Only (No Current Limit Slope)
b) Slope Compensation Configured for PWM and Current Limit
FIGURE 3. Slope Compensation Configuration
14
straints. Refer to the Applications Information section for more
details on configuring the RAMP pin for feed-forward voltage
mode control and peak current mode control.
Slope Pin
For duty cycles greater than 50% (25% for each phase), peak
current mode control is subject to sub-harmonic oscillation.
Sub-harmonic oscillation is normally characterized by observ-
ing alternating wide and narrow duty cycles. This can be
eliminated by adding an artificial ramp, known as slope com-
pensation, to the modulating signal at the RAMP pin. The
SLOPE pin provides a current source ramping from 0 to
100μA, at the frequency set by the RT resistor, for slope com-
pensation. The ramping current source at the SLOPE pin can
be utilized in a couple of different ways to add slope compen-
sation to the RAMP signal:
1) As shown in
be connected together through an appropriate resistor to the
CS pin. This configuration will inject current sense signal plus
slope compensation to the RAMP pin but CS pin will not see
any slope compensation. Therefore, in this scheme slope
compensation will not affect the current limit.
2) In a second configuration, as shown in
SLOPE, RAMP and CS pins can be tied together. In this con-
figuration the ramping current source from the SLOPE pin will
flow through the filter resistor and filter capacitor, therefore
both the CS pin and the RAMP pin will see the current sense
signal plus the slope compensation ramp. In this scheme, the
current limit is compensated by the slope compensation and
the current limit onset point will vary.
If slope compensation is not required for e.g. in feed-forward
voltage mode control, the SLOPE pin must be connected to
the AGND pin. When the RT pin is synched to an external
clock, it is recommended to disable the SLOPE pin and add
slope compensation externally by connecting an appropriate
resistor from the VCC pin to the CS pin. Please refer to the
Applications Information section for more details.
Figure
3(a), the SLOPE and RAMP pins can
Figure
3(b), the
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