lm5046sqx National Semiconductor Corporation, lm5046sqx Datasheet - Page 15

• Manufacturer Part Number: lm5046sqx
• Description: Phase-shifted Full-bridge Pwm Controller With Integrated Mosfet Drivers
• Manufacturer: National Semiconductor Corporation

Soft-Start
The soft-start circuit allows the power converter to gradually
reach a steady state operating point, thereby reducing the
start-up stresses and current surges. When bias is supplied
to the LM5046, the SS capacitor is discharged by an internal
MOSFET. When the UVLO, VCC and REF pins reach their
operating thresholds, the SS capacitor is released and is
charged with a 20µA current source. Once the SS pin voltage
crosses the 1V offset, SS controls the duty cycle. The PWM
comparator is a three input device; it compares the RAMP
signal against the lower of the signals between the soft-start
and the loop error signal. In a typical isolated application, as
the secondary bias is established, the error amplifier on the
secondary side soft-starts and establishes closed-loop con-
trol, steering the control away from the SS pin.
One method to shutdown the regulator is to ground the SS
pin. This forces the internal PWM control signal to ground,
reducing the output duty cycle quickly to zero. Releasing the
SS pin begins a soft-start cycle and normal operation re-
sumes. A second shutdown method is presented in the UVLO
section.
Gate Driver Outputs
The LM5046 provides four gate drivers: two floating high side
gate drivers HO1 and HO2 and two ground referenced low
side gate drivers LO1 and LO2. Each internal driver is capable
of sourcing 1.5A peak and sinking 2A peak. The low-side gate
drivers are powered directly by the VCC regulator. The HO1
and HO2 gate drivers are powered from a bootstrap capacitor
connected between BST1/BST2 and HS1/HS2 respectively.
An external diode connected between VCC (anode pin) and
BST (cathode pin) provides the high side gate driver power
by charging the bootstrap capacitor from VCC when the cor-
responding switch node (HS1/HS2 pin) is low. When the high
side MOSFET is turned on, BST1 rises to a peak voltage
equal to VCC + V
The BST and VCC capacitors should be placed close to the
pins of the LM5046 to minimize voltage transients due to par-
HS1
where V
HS1
is the switch node voltage.
15
asitic inductances since the peak current sourced to the MOS-
FET gates can exceed 1.5A. The recommended value of the
BST capacitor is 0.1μF or greater. A low ESR / ESL capacitor,
such as a surface mount ceramic, should be used to prevent
voltage droop during the HO transitions.
Figure 4
outputs. Initially, the diagonal HO1 and LO2 are turned-on to-
gether during the power transfer cycle, followed by the free-
wheel cycle, where HO1 and HO2 are kept on. In the
subsequent phase, the diagonal HO2 and LO1 are turned-on
together during the power transfer cycle, followed by a free-
wheel cycle, where LO1 and LO2 are kept on. The power
transfer mode is often called the active mode and the free-
wheel mode is often called as the passive mode. The dead-
time between the passive mode and the active mode, T
set by the RD1 resistor and the dead-time between the active
mode and the passive mode, T
Refer to the Applications Information section for more details
on the operation of the phase-shifted full-bridge topology.
If the COMP pin is open circuit, the outputs will operate at
maximum duty cycle. The maximum duty cycle for each
phase is limited by the dead-time set by the RD1 resistor. If
the RD1 resistor is set to zero then the maximum duty cycle
is slightly less than 50% due to the internally fixed dead-time.
The internally fixed dead-time is 30ns which does not vary
with the operating frequency. The maximum duty cycle for
each output can be calculated from the following equation:
Where, T
frequency of the oscillator. For example, if the oscillator fre-
quency is set at 400 kHz and the T
resistor is 60ns, the resulting D
PA
illustrates the sequence of the LM5046 gate-drive
is the time set by the RD1 resistor and F
AP
MAX
, is set by the RD2 resistor.
will be equal to 0.488.
PA
time set by the RD1
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OSC
is the
PA
, is