tmp88ps42ng TOSHIBA Semiconductor CORPORATION, tmp88ps42ng Datasheet - Page 123

• Manufacturer Part Number: tmp88ps42ng
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Example :Generating 1024 Hz pulse using TC6 (fc = 20.0 MHz)
12.3.2 8-Bit Event Counter Mode (TC5, 6)
12.3.3 8-Bit Programmable Divider Output (PDO) Mode (TC5, 6)
TC6CR<TC6S>
TC6 pin input
TTREG6
INTTC6 interrupt request
Counter
When a match between the up-counter and the TTREGj value is detected, an INTTCj interrupt is generated and
the up-counter is cleared. After being cleared, the up-counter restarts counting at the falling edge of the input
pulse to the TCj pin. Two machine cycles are required for the low- or high-level pulse input to the TCj pin.
Therefore, a maximum frequency to be supplied is fc/2
and the TTREGj value is detected, the logic level output from the
the up-counter is cleared. The INTTCj interrupt request is generated at the time. The logic state opposite to the
timer F/Fj logic level is output from the
TCjCR<TFFj>. Upon reset, the timer F/Fj value is initialized to 0.
In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj pin.
Note 1: In the event counter mode, fix TCjCR<TFFj> to 0. If not fixed, the
Note 2: In the event counter mode, do not change the TTREGj setting while the timer is running. Since TTREGj is
Note 3: j = 5, 6
This mode is used to generate a pulse with a 50% duty cycle from the
In the PDO mode, the up-counter counts up using the internal clock. When a match between the up-counter
To use the programmable divider output, set the output latch of the I/O port to 1.
Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running.
Note 2: When the timer is stopped during PDO output, the
Note 3: j = 5, 6
pulses.
not in the shift register configuration in the event counter mode, the new value programmed in TTREGj is in
effect immediately after the programming. Therefore, if TTREGi is changed while the timer is running, an
expected operation may not be obtained.
Since TTREGj is not in the shift register configuration in the programmable divider output mode, the new
value programmed in TTREGj is in effect immediately after programming. Therefore, if TTREGi is changed
while the timer is running, an expected operation may not be obtained.
stopped. To change the output status, program TCjCR<TFFj> after the timer is stopped. Do not change the
TCjCR<TFFj> setting upon stopping of the timer.
Example: Fixing the
CLR (TCjCR).3: Stops the timer.
CLR (TCjCR).7: Sets the
Figure 12-3 8-Bit Event Counter Mode Timing Chart (TC6)
?
0
LD
LD
LD
n
Setting port
(TTREG6), 3DH
(TC6CR), 00010001B
(TC6CR), 00011001B
1
PDOj
pin to the high level when the TimerCounter is stopped
PDOj
2
pin to the high level.
Match detect
Page 113
PDOj
n-1
n 0
pin. An arbitrary value can be set to the timer F/Fj by
: 1/1024
: Sets the operating clock to fc/2
: Starts TC6.
PDOj
4
Counter
clear
Hz in the NORMAL or IDLE mode.
1
pin holds the output status when the timer is
÷
2
7
/fc
2
Match detect
÷
PDOj
2 = 3DH
PDOj, PWMj
n-1
pin is switched to the opposite state and
PDOj
n
and
0
pin.
7
, and 8-bit PDO mode.
Counter
clear
PPGj
1
pins may output
2
TMP88PS42NG
0