tmp88ps42ng TOSHIBA Semiconductor CORPORATION, tmp88ps42ng Datasheet - Page 127

• Manufacturer Part Number: tmp88ps42ng
• Description: 8 Bit Microcontroller Tlcs-870/x Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Example :Setting the timer mode with source clock fc/2
12.3.5 16-Bit Timer Mode (TC5 and 6)
TC6CR<TC6S>
TTREG5
(Lower byte)
TTREG6
(Upper byte)
INTTC6 interrupt request
Internal
source clock
Counter
(fc = 20.0 MHz)
able to form a 16-bit timer.
timer is started by setting TC6CR<TC6S> to 1, an INTTC6 interrupt is generated and the up-counter is cleared.
After being cleared, the up-counter continues counting. Program the lower byte and upper byte in this order in
the timer register. (Programming only the upper or lower byte should not be attempted.)
Table 12-5 Source Clock for 16-Bit Timer Mode
In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 5 and 6 are cascad-
When a match between the up-counter and the timer register (TTREG5, TTREG6) value is detected after the
Note 1: In the timer mode, fix TCjCR<TFFj> to 0. If not fixed, the
Note 2: In the timer mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the
Note 3: j = 5, 6
DV1CK = 0
fc/2
fc/2
fc/2
fc/2
NORMAL, IDLE mode
Figure 12-6 16-Bit Timer Mode Timing Chart (TC5 and TC6)
11
?
shift register configuration in the timer mode, the new value programmed in TTREGj is in effect immediately
after programming of TTREGj. Therefore, if TTREGj is changed while the timer is running, an expected
operation may not be obtained.
7
5
3
?
Source Clock
0
n
m
DV1CK = 1
LDW
DI
SET
EI
LD
LD
LD
1
fc/2
fc/2
fc/2
fc/2
12
8
6
4
2
(TTREG5), 927CH
(EIRD). EF28
(TC5CR), 13H
(TC6CR), 04H
(TC6CR), 0CH
3
fc = 20 MHz
DV1CK = 0
102.4 μs
6.4 μs
1.6 μs
0.4 μs
Match
detect
7
mn-1
Page 117
[Hz], and generating an interrupt 240 ms later
Resolution
mn
0
fc = 20 MHz
DV1CK = 1
204.8 μs
12.8 μs
Counter
clear
3.2 μs
0.8 μs
: Sets the timer register (300 ms
: Enables INTTC6 interrupt.
:Sets the operating cock to fc/2
: Sets the 16-bit timer mode (upper byte).
: Starts the timer.
(lower byte).
1
PDOj
2
,
PWMj
fc = 20 MHz
DV1CK = 0
, and
419.4 ms
104.9 μs
26.2 μs
Match
detect
6.7 s
mn-1
Maximum Time Setting
PPGj
mn
7
pins may output a pulse.
÷
, and 16-bit timer mode
0
2
7
/fc = 927CH).
Counter
clear
1
fc = 20 MHz
DV1CK = 1
838.8 ms
209.7 ms
52.4 ms
13.4 s
2
TMP88PS42NG
0