atmega32u4-16mu ATMEL Corporation, atmega32u4-16mu Datasheet - Page 139

• Manufacturer Part Number: atmega32u4-16mu
• Description: Atmega32u4 8-bit Avr Microcontroller With 32k Bytes Of Isp Flash And Usb Controller
• Manufacturer: ATMEL Corporation

15.1.2
15.2
15.3
7766A–AVR–03/08
Timer/Counter Clock Sources
Counter Unit
Definitions
The Timer/Counter is clocked internally, via the prescaler. The Timer/Counter is inactive when
no clock source is selected. The clock source is referred to as the timer clock (clk
The double buffered Output Compare Register (OCR2A and OCR2B) are compared with the
Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-
erator to generate a PWM or variable frequency output on the Output Compare pins (OC2A and
OC2B).
set the Compare Flag (OCF2A or OCF2B) which can be used to generate an Output Compare
interrupt request.
Many register and bit references in this document are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 2. However, when using the register or bit
defines in a program, the precise form must be used, i.e., TCNT2 for accessing Timer/Counter2
counter value and so on.
The definitions in the table below are also used extensively throughout the section.
The Timer/Counter 2 can be clocked only by an internal synchronous clock source. The clock
source clk
caler, see
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
15-2
Figure 15-2. Counter Unit Block Diagram
Signal description (internal signals):
BOTTOM
MAX
TOP
shows a block diagram of the counter and its surrounding environment.
count
direction
clear
See “Output Compare Unit” on page 140.
T2
“Timer/Counter Prescaler” on page
is by default equal to the MCU clock, clk
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
The counter reaches the BOTTOM when it becomes zero (0x00).
The counter reaches the TOP when it becomes equal to the highest
value in the count sequence. The TOP value can be assigned to be the
fixed value 0xFF (MAX) or the value stored in the OCR2A Register. The
assignment is dependent on the mode of operation.
DATA BUS
TCNTn
Increment or decrement TCNT2 by 1.
Selects between increment and decrement.
Clear TCNT2 (set all bits to zero).
direction
count
clear
bottom
155.
Control Logic
for details. The compare match event will also
I/O
top
. For details on clock sources and pres-
TOVn
(Int.Req.)
clk
Tn
Prescaler
ATmega32U4
T2
).
clk
I/O
Figure
139