m30262f8gp Renesas Electronics Corporation., m30262f8gp Datasheet - Page 69

• Manufacturer Part Number: m30262f8gp
• Description: Renesas 16-bit Cmos Single-chip Microcomputer M16c Family / M16c/20 Series
• Manufacturer: Renesas Electronics Corporation.

Precautions for Interrupts
(5) Watchdog timer interrupt
(6) Rewrite the interrupt control register
• When the polarity of the INT
• Write to the watchdog timer start register after the watchdog timer interrupt occurs (initialize watchdog
• To rewrite the interrupt control register, do so at a point where an interrupt request for that register is not
(1) Changing a non-interrupt request bit
(2) Changing the interrupt request bit
When attempting to clear the interrupt request bit of an interrupt control register, the interrupt request bit
sometimes set to “1”. After changing the polarity, set the interrupt request bit to “0”. Figure 1.9.13
shows the procedure for changing the INT interrupt generate factor.
timer).
generated. If there is possibility of the interrupt request occur, disable the interrupt before rewriting the
interrupt control register. Some program examples are described as follow:
When changing an interrupt control register with interrupts enabled, please read the following precau-
tions on instructions used before changing the register.
register is being executed, there is a case that the interrupt request bit is not set and consequently the
interrupt is ignored. This will depend on the instruction. If this creates problems, use the instructions
below to change the register.
Instructions : AND, OR, BCLR, BSET
is not cleared sometimes. This will depend on the instruction. If this creates problems, use the instruc-
tions below to change the register.
Instructions : MOV
If an interrupt request for an interrupt control register is generated during an instruction to rewrite the
Example 1:
Example 2:
Example 3:
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
Preliminary Specifications Rev. 0.9
INT_SWITCH1:
INT_SWITCH2:
INT_SWITCH3:
Specifications in this manual are tentative and subject to change.
FCLR
AND.B
NOP
NOP
FSET
FCLR
AND.B
MOV.W MEM, R0
FSET
PUSHC FLG
FCLR
AND.B
POPC
I
#00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
I
I
#00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
I
I
#00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
FLG
0
, INT
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; Disable interrupts.
; Four NOP instructions are required when using HOLD function.
; Enable interrupts.
; Disable interrupts.
; Dummy read.
; Enable interrupts.
; Push Flag register onto stack
; Disable interrupts.
; Enable interrupts.
1,
INT
3
through INT
5
pins is changed, the interrupt request bit is
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M16C/26 Group
63