xr16v564 Exar Corporation, xr16v564 Datasheet - Page 13

• Manufacturer Part Number: xr16v564
• Description: 2.25v To 3.6v Quad Uart With 32-byte Fifo
• Manufacturer: Exar Corporation

REV. 1.0.1
loading or unloading the FIFO in a block sequence determined by the programmed trigger level. The following
table show their behavior. Also see
The V564 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. Caution: the XTAL1 input is not 5V
tolerant. For programming details, see
Divisor” on page 13.
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins. Typical oscillator connections are shown
in
generator for standard or custom rates. For further reading on oscillator circuit please see application note
DAN108 on EXAR’s web site.
Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The
prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide
the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further
divides this clock by a programmable divisor between 1 and (216 - 0.0625) in increments of 0.0625 (1/16) to
obtain a 16X or 8X or 4X sampling clock of the serial data rate. The sampling clock is used by the transmitter
for data bit shifting and receiver for data sampling. The BRG divisor (DLL, DLM and DLD registers) defaults to
F
2.7
2.8
IGURE
Figure
RXRDY#
TXRDY#
P
INS
5. T
Crystal Oscillator or External Clock Input
Programmable Baud Rate Generator with Fractional Divisor
5. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate
T
YPICAL
ABLE
LOW = 1 byte
HIGH = no data
LOW = THR empty
HIGH = byte in THR
(FIFO D
5: TXRDY#
FCR
C
RYSTAL
BIT
ISABLED
-0=0
C
AND
ONNECTIONS
)
RXRDY# O
LOW = at least 1 byte in FIFO
HIGH = FIFO empty
LOW = FIFO empty
HIGH = at least 1 byte in FIFO
Figure 20
“Section 2.8, Programmable Baud Rate Generator with Fractional
(DMA M
22-47pF
XTAL1
FCR B
C1
UTPUTS IN
through 25.
ODE
R=300K to 400K
IT
-3 = 0
D
14.7456
ISABLED
MHz
13
FIFO
2.25V TO 3.6V QUAD UART WITH 32-BYTE FIFO
FCR B
)
22-47pF
XTAL2
C2
AND
IT
HIGH to LOW transition when FIFO reaches the
trigger level, or timeout occurs
LOW to HIGH transition when FIFO empties
LOW = FIFO has at least 1 empty location
HIGH = FIFO is full
-0=1 (FIFO E
DMA M
ODE FOR
(DMA M
NABLED
FCR B
C
ODE
)
HANNELS
IT
XR16V564/564D
-3 = 1
E
NABLED
A-D
)