xr16v564 Exar Corporation, xr16v564 Datasheet - Page 15

• Manufacturer Part Number: xr16v564
• Description: 2.25v To 3.6v Quad Uart With 32-byte Fifo
• Manufacturer: Exar Corporation

REV. 1.0.1
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 32 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X/8X/4X
internal clock. A bit time is 16/8/4 clock periods. The transmitter sends the start-bit followed by the number of
data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are
reported in the Line Status Register (LSR bit-5 and bit-6).
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 32 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.9
2.9.1
Output Data
Required
1000000
100000
115200
153600
200000
225000
230400
250000
300000
400000
460800
500000
750000
921600
10000
19200
25000
28800
38400
50000
57600
75000
Rate
2400
4800
9600
400
Transmitter
T
ABLE
Transmit Holding Register (THR) - Write Only
6: T
YPICAL DATA RATES WITH A
D
16x Clock
(Decimal)
IVISOR FOR
52.0833
39.0625
26.0417
13.0208
156.25
78.125
9.7656
6.6667
6.5104
3.2552
1.6276
312.5
3750
3.75
625
150
7.5
1.5
60
30
20
15
6
5
3
2
O
BTAINABLE IN
312 8/16
156 4/16
78 2/16
52 1/16
39 1/16
26 1/16
D
9 12/16
6 11/16
3 12/16
1 10/16
7 8/16
6 8/16
3 4/16
1 8/16
V2550
3750
IVISOR
625
150
60
30
20
15
13
6
5
3
2
24 MH
DLM P
V
ALUE
Z CRYSTAL OR EXTERNAL CLOCK AT
15
ROGRAM
E
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(HEX)
2.25V TO 3.6V QUAD UART WITH 32-BYTE FIFO
DLL P
V
ALUE
A6
9C
4E
3C
1E
1A
71
38
96
34
27
14
D
ROGRAM
F
9
7
6
6
6
5
3
3
3
2
1
1
(HEX)
DLD P
V
ALUE
ROGRAM
C
B
C
A
16X S
0
0
8
4
0
2
0
1
1
0
1
0
0
0
8
8
0
0
4
0
0
8
XR16V564/564D
(HEX)
AMPLING
D
ATA
R
ATE
0.04
0.08
0.16
0.16
0.31
0.16
0.16
0.16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
E
RROR
(%)