xr16v564 Exar Corporation, xr16v564 Datasheet - Page 16

• Manufacturer Part Number: xr16v564
• Description: 2.25v To 3.6v Quad Uart With 32-byte Fifo
• Manufacturer: Exar Corporation

XR16V564/564D
2.25V TO 3.6V QUAD UART WITH 32-BYTE FIFO
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
The host may fill the transmit FIFO with up to 32 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
FIFO becomes empty. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set
when TSR/FIFO becomes empty.
F
F
2.9.2
2.9.3
IGURE
IGURE
7. T
8. T
Transmitter Operation in non-FIFO Mode
Transmitter Operation in FIFO Mode
RANSMITTER
RANSMITTER
16X or 8X or 4X Clock
Auto CTS Flow Control (CTS# pin)
(Xoff1/2 and Xon1/2 Reg.)
Auto Software Flow Control
Flow Control Characters
(DLD[5:4])
16X or 8X or 4X
O
O
( DLD[5:4] )
PERATION IN NON
PERATION IN
Clock
Data
Byte
Data Byte
Transmit
Transmit Shift Register (TSR)
FIFO
-FIFO M
AND
Transmit Data Shift Register
Transmit
Register
Holding
(THR)
F
LOW
ODE
(TSR)
Transmit
16
FIFO
C
ONTROL
M
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
ODE
THR Interrupt (ISR bit-1) falls
below the programmed Trigger
Level and then when becomes
bit-0=1
empty. FIFO is Enabled by FCR
M
S
B
L
S
B
TXNOFIFO1
TXFIFO1
REV. 1.0.1