a3p250 Actel Corporation, a3p250 Datasheet - Page 77

• Manufacturer Part Number: a3p250
• Description: Proasic3 Flash Family Fpgas With Optional Soft Arm Support
• Manufacturer: Actel Corporation

Figure 2-16 • Input Register Timing Diagram
Table 2-88 • Input Data Register Propagation Delays
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
Enable
Data
Clear
CLK
Preset
Out_1
ICLKQ
ISUD
IHD
ISUE
IHE
ICLR2Q
IPRE2Q
IREMCLR
IRECCLR
IREMPRE
IRECPRE
IWCLR
IWPRE
ICKMPWH
ICKMPWL
For specific junction temperature and voltage supply levels, refer to
values.
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Enable Setup Time for the Input Data Register
Enable Hold Time for the Input Data Register
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width HIGH for the Input Data Register
Clock Minimum Pulse Width LOW for the Input Data Register
Input Register
Timing Characteristics
Commercial-Case Conditions: T
50%
50%
t
1
ISUE
t
IHE
50%
50%
t
ISUD
0
t
t
ICLKQ
IHD
50%
Description
50%
J
50%
= 70°C, Worst-Case V
t
IWPRE
t
IPRE2Q
50%
50%
v1.2
t
IRECPRE
50%
t
ICLR2Q
50%
t
IWCLR
50%
50%
CC
50%
= 1.425 V
t
IRECCLR
ProASIC3 DC and Switching Characteristics
Table 2-6 on page 2-6
50%
t
ICKMPWH
0.24 0.27 0.32 0.38
0.26 0.30 0.35 0.42
0.00 0.00 0.00 0.00
0.37 0.42 0.50 0.60
0.00 0.00 0.00 0.00
0.45 0.52 0.61 0.73
0.00 0.00 0.00 0.00
0.22 0.25 0.30 0.36
0.22 0.25 0.30 0.36
0.22 0.25 0.30 0.36
0.22 0.25 0.30 0.36
0.36 0.41 0.48 0.57
0.32 0.37 0.43 0.52
0.45 0.52 0.61 0.73
0.00 0.00 0.00 0.00
t
–2
IREMPRE
50%
–1 Std. –F Units
50%
t
ICKMPWL
for derating
50%
t
50%
IREMCLR
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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