a3p250 Actel Corporation, a3p250 Datasheet - Page 8

• Manufacturer Part Number: a3p250
• Description: Proasic3 Flash Family Fpgas With Optional Soft Arm Support
• Manufacturer: Actel Corporation

ProASIC3 Device Family Overview
Figure 1-2 • ProASIC3 Device Architecture Overview with Four I/O Banks (A3P250, A3P600, and A3P1000)
1 -4
Decryption
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input
logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate
flash switch interconnections. The versatility of the ProASIC3 core tile as either a three-input
lookup table (LUT) equivalent or as a D-flip-flop/latch with enable allows for efficient use of the
FPGA fabric. The VersaTile capability is unique to the Actel ProASIC family of third-generation
architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy.
Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable
interconnect programming. Maximum core utilization is possible for virtually any design.
In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V)
programming of ProASIC3 devices via an IEEE 1532 JTAG interface.
VersaTiles
The ProASIC3 core consists of VersaTiles, which have been enhanced beyond the ProASIC
tiles. The ProASIC3 VersaTile supports the following:
ISP AES
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All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
User Nonvolatile
FlashROM
Bank 0
Bank 2
v1.0
Charge Pumps
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block
(A3P600 and A3P1000)
I/Os
CCC
VersaTile
PLUS®
core