as7c33256ntd18b ETC-unknow, as7c33256ntd18b Datasheet
as7c33256ntd18b
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as7c33256ntd18b Summary of contents
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... CLK R/W BWa Control BWb logic LBO ZZ CLK 18 18 Data Q D Input Register CLK CLK CEN OE -200 5 200 3.0 375 135 30 Alliance Semiconductor AS7C33256NTD18B CLK 256K x 18 SRAM Array CLK Output Register [a:b] -166 -133 Units 6 7.5 MHz 166 133 3 350 ...
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... Mode PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD NTD-PL NTD-PL NTD-PL NTD-FT NTD-FT NTD- Alliance Semiconductor AS7C33256NTD18B Speed 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/ ...
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... DQb4 19 DQb5 V 20 DDQ V 21 SSQ 22 DQb6 23 DQb7 24 DQPb SSQ V 27 DDQ v.1.5 2/8/05; ® TQFP 14x20mm Alliance Semiconductor AS7C33256NTD18B DDQ V 76 SSQ DQPa 73 DQa7 72 DQa6 71 V SSQ 70 V DDQ 69 DQa5 68 DQa4 ...
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... Functional description The AS7C33256NTD18B family is a high performance CMOS 4 Mbit synchronous Static Random Access Memory (SRAM) organized as 262,144 words × 18 bits and incorporates a LATE LATE Write. This variation of the 4Mb sychronous SRAM uses the No Turnaround Delay (NTD Write operation that improves bandwidth over pipeline burst devices normal pipeline burst device, the write data, command, and address are all applied to the device on the same clock edge ...
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... ZZI Starting Address First increment Second increment Third increment Alliance Semiconductor AS7C33256NTD18B . The duration of SB2 Linear burst order (LBO = ...
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... L External NOP/WRITE ABORT (Begin Burst) High Next Current Alliance Semiconductor AS7C33256NTD18B Operation DESELECT Cycle High-Z DESELECT Cycle High-Z DESELECT Cycle High-Z CONTINUE DESELECT Cycle High-Z READ Cycle (Begin Burst) READ Cycle (Continue Burst) DUMMY READ (Continue Burst) ...
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... Symbol Min Nominal V 3.135 3 3.135 3.3 DDQ Vss 0 0 Symbol Min Nominal V 3.135 3 2.375 2.5 DDQ Vss 0 0 Alliance Semiconductor AS7C33256NTD18B Burst Dsel Burst Burst Min Max Unit –0.5 +4.6 –0 0.5 DD –0 0.5 DDQ – 1.8 – –65 +150 o –65 +135 Max Unit 3 ...
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... Deselected < Max IL Deselected < 0.2V, ≤ 0.2V or ≥ V all V – 0. ≥ V Deselected Max DD ≤ ≥ V all Alliance Semiconductor AS7C33256NTD18B Min Max Unit -2 2 µA DD < µA DDQ +0.3 DDQ -0.3** 0 ...
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... CENS t 1.4 – 1.5 ADVS t 0.4 – 0 0.4 – 0 0.4 – 0 0.4 – 0.5 ADVH t 0.4 – 0.5 CENH t 0.4 – 0.5 CSH Conditions Symbol ZZ > SB2 t PDS t PUS t ZZI t RZZI Alliance Semiconductor AS7C33256NTD18B -133 Min Max Unit Notes - 133 MHz - 2,3 2,3,4 - 4.0 ns 2,3,4 - 4.0 ns 2,3 ...
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... Falling input HZOE OE Q(A1) Q(A2) Q(A2Y‘01) Read Continue Continue Continue Q(A2) Read Read Q(A2Y‘10) Q(A2Y‘01) Q(A2Y‘11) Alliance Semiconductor AS7C33256NTD18B Undefined t CYC A3 Q(A2Y‘10) Q(A3) Q(A2Y‘11) Continue Inhibit Read Read Read Clock Q(A3) Q(A3Y‘01 HLZC ...
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... HZOE Dout Q(n-2) Q(n-1) Write DSEL D(A1) v.1.5 2/8/05; ® D(A1) D(A2) D(A2Y‘01) Write Continue Continue Continue D(A2) Write Write Write D(A2Y‘10) D(A2Y‘01) D(A2Y‘11) Alliance Semiconductor AS7C33256NTD18B t CYC D(A3) D(A2Y‘10) D(A2Y‘11) Continue Inhibit Write Write Clock D(A3) D(A3Y‘01 ...
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... Note: Ý = XOR when LBO = high/no connect. Ý = ADD when LBO = low. BW[a:d] is don’t care. v.1.5 2/8/05; ® LZC OH D(A1) D(A2) Q(A3) D(A2Ý01) Burst Burst Read Read Write Q(A3) Read Q(A4) D(A2Ý01) Q(A4Ý01) Alliance Semiconductor AS7C33256NTD18B t CYC HZC D(A5) Q(A6) Q(A4) Q(A4Ý01) t HZOE t LZOE Read Write Write D(A5) Q(A6) D(A7 DSEL ...
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... Address A1 D/Q Command Read Burst Q(A1) Q(A1Ý01) Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low low. v.1.5 2/8/05; ® A2 Q(A1Ý01) Q(A1) Q(A1Ý10) STALL Burst DSEL Burst Q(A1Ý10) DSEL Alliance Semiconductor AS7C33256NTD18B A3 D(A2) Burst Write Write Burst NOP NOP D(A2) D(A2Ý10) D(A2Ý01) D(A3 ...
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... Timing waveform of snooze mode CLK ZZ setup cycle ZZ t ZZI I supply I SB2 All inputs Deselect or Read Only (except ZZ) Dout v.1.5 2/8/05; ® t PUS ZZ recovery cycle t RZZI Deselect or Read Only High-Z Alliance Semiconductor AS7C33256NTD18B Normal operation Cycle ...
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... CLK. All other synchronous at any given temper- LZC inputs must meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled. Alliance Semiconductor AS7C33256NTD18B Thevenin equivalent: +3.3V for 3.3V I/O; /+2.5V for 2.5V I/O 319Ω / 1667Ω D ...
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... Package Dimensions: 100-pin quad flat pack (TQFP) TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e 0.65 nominal Hd 15.90 16.10 He 21.90 22.10 L 0.45 0.75 L1 1.00 nominal a 0° 7° Dimensions in millimeters v.1.5 2/8/05; ® Alliance Semiconductor AS7C33256NTD18B b e α ...
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... Ordering information Width Package ×18 TQFP AS7C33256NTD18B-200TQC ×18 TQFP AS7C33256NTD18B-200TQI Note: Add suffix ‘N’ to the above part numbers for lead free parts (Ex AS7C33256NTD18B-166TQCN) Part numbering guide AS7C 33 256 1.Alliance Semiconductor SRAM prefix 2.Operating voltage: 33=3.3V 3.Organization: 256=256K TM NTD =No Turn-around Delay, Pipelined mode. ...
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... Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. AS7C33256NTD18B ® Copyright © Alliance Semiconductor All Rights Reserved Part Number: AS7C33256NTD18B Document Version: v.1.5 ...