as7c33256ntd18b ETC-unknow, as7c33256ntd18b Datasheet - Page 4

• Manufacturer Part Number: as7c33256ntd18b
• Manufacturer: ETC-unknow

Functional description
The AS7C33256NTD18B family is a high performance CMOS 4 Mbit synchronous Static Random Access Memory (SRAM)
organized as 262,144 words × 18 bits and incorporates a LATE LATE Write.
This variation of the 4Mb sychronous SRAM uses the No Turnaround Delay (NTD
Write operation that improves bandwidth over pipeline burst devices. In a normal pipeline burst device, the write data,
command, and address are all applied to the device on the same clock edge. If a Read command follows this Write command,
the system must wait for two 'dead' cycles for valid data to become available. These dead cycles can significantly reduce
overall bandwidth for applications requiring random access or Read-Modify-Write operations.
NTD
pipeline (flowthrough) read latency. Write data is applied two cycles after the Write command and address, allowing the Read
pipeline to clear. With NTD
Assert R/W low to perform Write cycles. Byte Write enable controls write access to specific bytes, or can be tied low for full
18 bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is
applied to the device two clock cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled
for write operations; it can be tied low for normal operations. Outputs go to a high impedance state when the device is de-
selected by any of the three chip enable inputs (refer to Synchronous truth table on page 6). In pipeline mode, a two cycle
deselect latency allows pending read or write operations to be completed.
Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip
select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any
device operations, including burst, can be stalled using the CEN=1 the clock enable input.
The AS7C33256NTD18B operates with a 3.3V ± 5% power supply for the device core (V
power supply (V
package.
TQFP Capacitance
*Guranteed not tested
TQFP thermal resistance
1 This parameter is sampled
Input capacitance
I/O capacitance
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to top of case)
2/8/05;
™
devices use the memory bus more efficiently by introducing a write 'latency' which matches the two (one)cycle
Parameter
Description
v.1.5
DDQ
1
) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin 14×20 mm TQFP
1
™
, Write and Read operations can be used in any order without producing dead bus cycles.
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
Symbol
C
C
I/O
IN
*
*
per EIA/JESD51
Conditions
Alliance Semiconductor
Test conditions
V
in
V
= V
in
= 0V
out
= 0V
®
1–layer
4–layer
™
Min
) architecture, featuring an enhanced
Symbol
-
-
θ
θ
θ
JA
JA
JC
DD
AS7C33256NTD18B
). DQ circuits use a separate
Typical
Max
40
22
5
7
8
P. 4 of 18
Units
°C/W
°C/W
°C/W
Unit
pF
pF