as7c33256ntd18b ETC-unknow, as7c33256ntd18b Datasheet - Page 5

• Manufacturer Part Number: as7c33256ntd18b
• Manufacturer: ETC-unknow

Signal descriptions
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, I
is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during t
MODE.
Burst order
CE0, CE1,
A, A0, A1
ADV/LD
BW[a,b]
Second increment
DQ[a,b]
Signal
Starting address
Third increment
First increment
CLK
CEN
LBO
R/W
CE2
2/8/05;
OE
NC
ZZ
v.1.5
Interleaved burst order (LBO = 1)
I/O Properties Description
I/O
I
I
I
I
I
I
I
I
I
-
I
CLOCK
ASYNC
ASYNC
STATIC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
A1 A0
PUS
0 0
0 1
1 0
1 1
-
, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE
Selects Burst mode. When tied to V
order. When driven Low, device follows linear Burst order. This signal is internally pulled
High.
Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock.
Clock enable. When de-asserted HIGH, the clock input signal is masked.
Address. Sampled when all chip enables are active and ADV/LD is asserted.
Data. Driven as output when the chip is enabled and OE is active.
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted.
Are ignored when ADV/LD is HIGH.
Advance or Load. When sampled HIGH, the internal burst address counter will increment
in the order defined by the LBO input value. When LOW, a new address is loaded.
A HIGH during LOAD initiates a READ operation. A LOW during LOAD initiates a
WRITE operation. Is ignored when ADV/LD is HIGH.
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
Asynchronous output enable. I/O pins are not driven when OE is inactive.
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
No connects.
A1 A0
0 1
0 0
1 1
1 0
SB2
is guaranteed after the time t
A1 A0
1 0
1 1
0 0
0 1
Alliance Semiconductor
A1 A0
1 0
1 1
0 1
0 0
Second increment
Starting Address
Third increment
ZZI
First increment
®
DD
is met. After entering SNOOZE MODE, all inputs except ZZ
or left floating, device follows interleaved Burst
Linear burst order (LBO = 0)
A1 A0
0 0
0 1
1 0
1 1
AS7C33256NTD18B
A1 A0
0 1
1 0
1 1
0 0
SB2
A1 A0
1 0
1 1
0 0
0 1
. The duration of
P. 5 of 18
A1 A0
0 0
0 1
1 0
1 1