as7c33256ntd18b ETC-unknow, as7c33256ntd18b Datasheet - Page 15

• Manufacturer Part Number: as7c33256ntd18b
• Manufacturer: ETC-unknow

AC test conditions
• Output Load: see Figure B, except for t
• Input pulse level: GND to 3V. See Figure A.
• Input rise and fall time (Measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
1
2
3
4
5
Notes:
+3.0V
GND
2/8/05;
For test conditions, see AC Test Conditions, Figures A, B, C.
This parameter measured with output load condition in Figure C
This parameter is sampled and not 100% tested.
t
ature and voltage.
t
have stopped driving.
HZOE
HZCN
Figure A: Input waveform
10%
90%
is less than t
v.1.5
is a
‘no load’ parameter to indicate exactly when SRAM outputs
LZOE
; and t
90%
10%
HZC
is less than t
LZC
D
, t
out
LZC
LZOE
at any given temper-
Figure B: Output load (A)
, t
Alliance Semiconductor
HZOE
Z
0
=50
, t
HZC
Ω
see Figure C.
50
6
7
30 pF*
Ω
®
t
VIL
This is a synchronous device. All addresses must meet the specified
setup and hold times for all rising edges of CLK. All other synchronous
inputs must meet the setup and hold times with stable logic levels for all
rising edges of CLK when chip is enabled.
CH
V
measured as HIGH above VIH, and t
L
=1.5V
353Ω / 1538Ω
D
OUT
Figure C: Output load (B)
AS7C33256NTD18B
Thevenin equivalent:
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
319Ω / 1667Ω
5 pF*
GND
CL
measured as LOW below
*including scope
and jig capacitance
P. 15 of 18