s71pl129ja0 Meet Spansion Inc., s71pl129ja0 Datasheet - Page 12

• Manufacturer Part Number: s71pl129ja0
• Description: Stacked Multi-chip Product Mcp Flash Memory And Psram 128 Megabit 8m X 16-bit Cmos 3.0 Volt-only Simultaneous Operation, Page Mode Flash Memory With 64/32/16 Megabit 4m/2m/1m X 16-bit Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

S29PL129J for MCP
128 Megabit (8 M x 16-Bit) 
CMOS 3.0 Volt-only, Simultaneous Read/Write 
Flash Memory with Enhanced VersatileIO
Datasheet
Distinctive Characteristics
Architectural Advantages
T
T
T
T
T
T
T
T
T
T
T
128 Mbit Page Mode devices
— Page size of 8 words: Fast page read access from
Single power supply operation
— Full Voltage range: 2.7 to 3.6 volt read, erase, and
Dual Chip Enable inputs (only in PL129J)
— Two CE# inputs control selection of each half of the
Simultaneous Read/Write Operation
— Data can be continuously read from one bank while
— Zero latency switching from write to read operations
FlexBank Architecture
— 4 separate banks, with up to two simultaneous
— CE#1 controlled banks:
— CE#2 controlled banks:
Enhanced VersatileI/O
— Output voltage generated and input voltages
Secured Silicon Sector region
— Up to 128 words accessible through a command
— Up to 64 factory-locked words
— Up to 64 customer-lockable words
Bot h top and bott om boot blocks in one device
Manufactured on 110 nm process technology
Data Retention: 20 years typical
Cycling Endurance: 1 million cycles per sector
typical
random locations within the page
program operations for battery-powered applications
memory space
executing erase/ program functions in another bank
operations per device
Bank 1A:
- 16Mbit (4Kw x 8 and 32Kw x 31)
Bank 1B:
- 48Mbit (32Kw x 96)
Bank 2A:
- 48 Mbit (32Kw x 96)
Bank 2B:
- 16Mbit (4Kw x 8 and 32Kw x 31)
tolerated on all control inputs and I / Os is determined
by the voltage on the V
sequence
Publication Number S29PL129J_MCP_00
TM
IO
(V
pin
IO
) Control
Revision A
Performance Characteristics
T
T
Software Features
T
T
T
T
Hardware Features
T
T
T
T
TM
High Performance
— P age access times as fast as 20 ns
— Random access times as fast as 55 ns
Power consumption (typical values at 10 MHz)
— 45 mA active read current
— 17 mA program/erase current
— 0.2 µA typical standby mode current
Software command-set compatible with JEDEC
42.4 st andard
— Backward compatible with Am29F, Am29LV ,
CFI (Common Flash Interface) compliant
— Provides device-specific information to the system,
Erase Suspend / Erase Resume
— Suspends an erase operation to allow read or
Unlock Bypass Program command
— Reduces overall programming time when issuing
Ready/Busy# pin (RY/ BY#)
— Provides a hardware method of detecting program or
Hardware reset pin (RESET# )
— Hardware method to reset the device to reading
WP# / ACC ( Write Protect/ Accelerat ion) input
— At V
— At V
— At V
Persist ent Sect or Protect ion
— A command sector protection method to lock
Amendment 0
Control
Am29DL, and AM29PDL families and MBM29QM/RM,
MBM29LV , MBM29DL, MBM29PDL families
allowing host software to easily reconfigure for
different Flash devices
program operations in other sectors of same bank
multiple program command sequences
erase cycle completion
array data
last two 4K word sectors.
factory setting
combinations of individual sectors and sector groups
IL
IH
HH
, hardware level protection for the first and
, allows removal of sector protection
, provides accelerated programming in a
Issue Date June 4, 2004
INFORMATION
ADVANCE