th50vsf3580aasb TOSHIBA Semiconductor CORPORATION, th50vsf3580aasb Datasheet

th50vsf3580aasb

Manufacturer Part Number

th50vsf3580aasb

Description

Sram Flash Memory Mixed Multi-chip Package

Manufacturer

TOSHIBA Semiconductor CORPORATION

Datasheet

1.TH50VSF3580AASB.pdf (50 pages)

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TENTATIVE

SRAM AND FLASH MEMORY MIXED MULTI-CHIP PACKAGE

DESCRIPTION

33,554,432-bit flash memory. The CIOS and CIOF inputs can be used to select the optimal memory configuration.

The power supply. FLASH MEMORY a Simultaneous Read/Write operation so that data can be read during a Write

or Erase operation. The TH50VSF3580/3581AASB can range from 2.7 V to 3.3 V. The TH50VSF3580/3581AASB is

available in a 69-pin BGA package, making it suitable for a variety of design applications.

FEATURES

•

PIN ASSIGNMENT

•

• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general

• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal

The TH50VSF3580/3581AASB is a mixed multi-chip package containing a 8,388,608-bit Full CMOS SRAM and a

can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,

when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid

situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to

property.

In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most

recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide

for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..

equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are

neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or

failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control

instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control

instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document

shall be made at the customer’s own risk.

Power supply voltage

Data retention supply voltage

Current consumption

Block erase architecture for flash memory

Organization

Case: CIOF = V

CIOF

Operating: 45 mA maximum (CMOS level)

Standby:

8 × 8 Kbytes

63 × 64 Kbytes

CCs

CCf

CCs

CIOS

= 2.7 V~3.3 V

= 1.5 V~3.3 V

CEF

2,097,152 words of 16 bits

4,194,304 words of 8 bits

10 µA maximum (SRAM CMOS level)

10 µA maximum (FLASH)

TOSHIBA MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS

DQ0

DQ8

, CIOS = V

Flash Memory

DQ10

DQ1

DQ9

DQ2

A18

A17

(TOP VIEW)

RESET

DQ11

DQ3

(×16, ×16)

CCf

/ACC

CE2S

CIOS

DQ4

A20

524,288 words of 16 bits

1,048,576 words of 8 bits

CCs

DQ13 DQ15 CIOF

DQ12

DQ6

DQ5

A19

A10

SRAM

DQ14

DQ7

A12

A13

A14

A11

A15

A16

•

Function mode control for flash memory

Flash memory functions

Erase and Program cycle for flash memory

Boot block architecture for flash memory

Package

PIN NAMES

Compatible with JEDEC-standard commands

Simultaneous Read/Write operations

Auto-Program

Auto Chip Erase, Auto Block Erase

Auto Multiple-Block Erase

Program Suspend/Resume

Block-Erase Suspend/Resume

Data Polling/Toggle Bit function

Block Protection/Boot Block Protection

Automatic Sleep, Hidden ROM Area Supports

Common Flash Memory Interface (CFI)

Byte/Word Mode

TH50VSF3580AASB: Top boot block

TH50VSF3581AASB: Bottom boot block

P-FBGA69-1209-0.80A3: 0.31 g (typ.)

DQ0~DQ15

LB , UB

A0~A21

RESET

cycles (typical)

A12S

CIOS

A12F

CIOF

CEF

CCs

CCf

/ACC

, CE2S Chip Enable Inputs for SRAM

TH50VSF3580/3581AASB

A18 Input for SRAM

Data Inputs/Outputs

Chip Enable Input for Flash Memory

Output Enable Input

Write Enable Input

Data Byte Control Input

Ready/Busy Output

Hardware Reset Input

Write Protect/Program Acceleration Input

Word Enable Input for SRAM

Word Enable Input for Flash Memory

Power Supply for SRAM

Power Supply for Flash Memory

Ground

Not Connected

Don’t Use

Address Inputs

A12 Input for SRAM

A12 Input for Flash Memory

2001-03-06 1/50

000707EBA2

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