m36l0t7060b2 STMicroelectronics, m36l0t7060b2 Datasheet

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... PPF ■ Electronic signature – Manufacturer Code: 20h – Device Code (Top Flash Configuration) M36L0T7060T2: 88C4h – Device Code (Bottom Flash Configuration) M36L0T7060B2: 88C5h ■ ECOPACK® packages available Flash memory ■ Synchronous / Asynchronous Read – Synchronous Burst Read mode: 52 MHz – ...

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... DDF 2.18 V supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 CCP 2.19 V supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DDQ 2.20 V Program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PPF 2.21 V ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/ M36L0T7060T2, M36L0T7060B2 ...

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... M36L0T7060T2, M36L0T7060B2 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contents 3/22 ...

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... List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 5. Device capacitance Table 6. Stacked TFBGA88 8x10 mm - 8x10 active ball array, 0.8 mm pitch, package data Table 7. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4/22 M36L0T7060T2, M36L0T7060B2 ...

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... M36L0T7060T2, M36L0T7060B2 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. TFBGA connections (top view through package Figure 3. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 4. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 5. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 6. Stacked TFBGA88 8x10 mm - 8x10 active ball array, 0.8 mm pitch, bottom view outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 List of figures ...

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... Description 1 Description The M36L0T7060T2 and M36L0T7060B2 combine two memory devices in a multichip package: ● a 128-Mbit, Multiple Bank, Multilevel, Burst, Flash memory, the M58LT128HT or M58LT128HB ● a 64-Mbit PseudoSRAM, the M69KW096B. The purpose of this document is to describe how the two memory components operate with respect to each other ...

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... M36L0T7060T2, M36L0T7060B2 Table 1. Signal names (1) A0-A22 DQ0-DQ15 V DDF V DDQ V PPF CCP NC DU Flash memory signals WAIT F PSRAM signals A22 is not connected to the PSRAM component. Address Inputs Common Data Input/Output ...

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... DQ8 DQ2 DQ10 DQ5 DQ0 DQ1 DQ3 DQ12 G F DQ9 DQ11 DQ4 CCP DDQ V DDF M36L0T7060T2, M36L0T7060B2 A21 A11 K F A22 A12 A13 A20 A10 A15 A8 A14 A16 DQ13 WAIT F NC ...

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... M36L0T7060T2, M36L0T7060B2 2 Signal descriptions See Figure 1: Logic diagram connected to this device. 2.1 Address inputs (A0-A22) Addresses A0-A21 are common inputs for the Flash memory and the PSRAM components. The other line (A22 input for the Flash memory component only. The Address Inputs select the cells in the memory array to access during Bus Read operations ...

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... It can be configured to be active during the wait cycle or one clock IL signal is not gated by Output Enable activates the memory state machine, address and M36L0T7060T2, M36L0T7060B2 , Lock-Down is disabled IH , the IL . Latch the same time ...

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... M36L0T7060T2, M36L0T7060B2 2.12 PSRAM Chip Enable input (E2 The Chip Enable, E2 This is the lowest power mode. 2.13 PSRAM Write Enable (W The Write Enable, W 2.14 PSRAM Output Enable (G The Output Enable, G cycles to be achieved with the common I/O data bus. 2.15 PSRAM Upper Byte Enable (UB The Upper Byte Enable, UB DQ15 from the upper part of the selected address during a Write or Read operation ...

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... In this condition V PPH decoupled with a 0.1 µF ceramic capacitor close to the pin PPF circuit. The PCB track widths should be program and erase currents. PPF M36L0T7060T2, M36L0T7060B2 ) V is seen as a control input. In this PPF PPF ) and the DDF ...

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... M36L0T7060T2, M36L0T7060B2 3 Functional description The PSRAM and Flash memory components have separate power supplies but share the same grounds. They are distinguished by three Chip Enable inputs: E memory and E1 P Recommended operating conditions do not allow more than one device to be active at a time. The most common example is simultaneous read operations in the Flash memory and the PSRAM which would result in a data bus contention ...

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... but must valid before the read or write operation. Controlled Write timing), or cycle time of the previous operation cycle is satisfied. P M36L0T7060T2, M36L0T7060B2 DQ0 A21 DQ7 Data Out Hi ...

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... M36L0T7060T2, M36L0T7060B2 4 Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied ...

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... Input and Output Timing Ref. Voltages Figure 4. AC measurement I/O waveform 16/22 conditions. Designers should check that the Flash memories Min 1.7 – 2.7 8.5 –0.4 – DDQ 0V M36L0T7060T2, M36L0T7060B2 PSRAM Max Min Max 2.0 – – – 2.7 3.5 3.5 – – 9.5 – – V +0.4 – – DDQ 85 – ...

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... M36L0T7060T2, M36L0T7060B2 Figure 5. AC measurement load circuit Table 5. Device capacitance Symbol C Input Capacitance IN C Output Capacitance OUT 1. Sampled only, not 100% tested. Please refer to the M58LT128HTB and M69KW096B datasheets for further DC and AC characteristic values and illustrations DDF DDQ DEVICE UNDER TEST 0.1µ ...

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... The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK trademark. ECOPACK specifications are available at: www.st.com. Figure 6. Stacked TFBGA88 8x10 mm - 8x10 active ball array, 0.8 mm pitch, bottom view outline Drawing is not to scale. 18/ BALL "A1" FE FE1 M36L0T7060T2, M36L0T7060B2 e b ddd A2 A1 BGA-Z42 ...

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... M36L0T7060T2, M36L0T7060B2 Table 6. Stacked TFBGA88 8x10 mm - 8x10 active ball array, 0.8 mm pitch, package data Symbol ddd E 10.000 FE1 SD SE millimeters Typ Min Max 1.200 0.200 0.850 0.350 0.300 0.400 8.000 7.900 8.100 5.600 0.100 9.900 10.100 7.200 8 ...

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... Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 20/22 M36 2.7 to 3.5 V DDQ CCP M36L0T7060T2, M36L0T7060B2 ZAQ F ...

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... M36L0T7060T2, M36L0T7060B2 8 Revision history Table 8. Document revision history Date 30-May-2006 20-Apr-2007 Revision 0.1 Initial release. Document status changed from Target Specification to Preliminary Data. 1 Updated DDF CCP Section 2.7: Flash Reset (RP Revision history Changes and V voltage ranges. DDQ ) updated. F 21/22 ...

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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 22/22 Please Read Carefully: © 2007 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com M36L0T7060T2, M36L0T7060B2 ...