m36l0t7060b2 STMicroelectronics, m36l0t7060b2 Datasheet - Page 14

• Manufacturer Part Number: m36l0t7060b2
• Description: 128 Mbit Multiple Bank, Multilevel, Burst Flash Memory And 64 Mbit 4 Mb X16 Psram, Multichip Package
• Manufacturer: STMicroelectronics

Functional description
Table 2.
1. X = Don't care.
2. WAIT signal polarity is configured using the Set Configuration Register command. See the M58LT128HTB datasheet for
3. L
4. Depends on G
5. Deep Power-Down mode can be entered from Standby state and all DQ pins are in High-Z state.
6. A0 to A21 can be either V
7. G
14/22
Flash Read
Flash Write
Flash Address
Latch
Flash Output
Disable
Flash Standby
Flash Reset
Deep Power-
Down
Standby
(Deselected)
Output Disable
No Read
Upper Byte
Read
Lower Byte
Read
Word Read
No Write
Upper Byte
Write
Lower Byte
Write
Word Write
Operation
details.
a- Write pulse is initiated by E1
b- G stays V
F
P
(5)
can be tied to V
can be V
Operating modes
IL
IL
F
during the entire Write cycle.
during the Write operation if the following conditions are satisfied:
.
V
V
V
V
V
E
Any Flash memory mode is allowed
X
IH
IL
IL
IL
IL
F
IH
Flash memory must be disabled
if the valid address has been previously latched.
V
V
V
G
X
X
X
IH
IH
IL
F
IH
V
V
V
W
V
or V
X
X
IH
IH
IH
IL
F
P
IL
(E1
V
V
but must valid before the read or write operation.
V
(1)
L
IL
IL
X
X
X
P
IL
F
(3)
(3)
Controlled Write timing), or cycle time of the previous operation cycle is satisfied.
RP
V
V
V
V
V
V
IH
IH
IH
IH
IH
IL
F
WAIT
Hi-Z
Hi-Z
Hi-Z
F
(2)
E2
V
V
V
IH
IH
IL
P
Any PSRAM mode is allowed
E1
V
V
PSRAM must be disabled
X
IH
IL
P
W
V
V
X
X
IH
IL
P
V
V
G
V
IH
X
X
IH
IL
P
(7)
M36L0T7060T2, M36L0T7060B2
LB
V
V
V
V
V
V
V
V
V
X
X
X
IH
IH
IH
IH
IH
IL
IL
IL
IL
P
, UB
V
V
V
V
V
V
V
V
V
X
X
X
IH
IH
IH
IH
IH
IL
IL
IL
IL
P
Valid
A21
(6)
X
X
Output
Output
Invalid
Invalid
DQ0-
Input
Input
Data
Data
Data
Data
DQ7
Hi-Z
Hi-Z
Hi-Z
Data Out or
Data Out
Data In
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Output
Output
(4)
Invalid
Invalid
DQ15
DQ8-
Input
Input
Data
Data
Data
Data
Hi-Z
Hi-Z
Hi-Z