k4t51043qb-gce6 Samsung Semiconductor, Inc., k4t51043qb-gce6 Datasheet - Page 17

• Manufacturer Part Number: k4t51043qb-gce6
• Description: 512mb B-die Ddr2 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

512Mb B-die DDR2 SDRAM
Operating Temperature Condition
Note :
Input DC Logic Level
Input AC Logic Level
AC Input Test Conditions
Note :
V
V
SLEW
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM.
2. The operation temperature range are the temperature where all DRAM specification will be supported.
1. Setup (tIS & tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vih(dc)min and the
2. Hold (tIH & tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc)max and the first
REF
SWING(MAX)
Symbol
Symbol
Symbol
Symbol
first crossing of Vih(ac)min. Setup (tIS & tDS) nominal slew rate for a falling signal is defined as the slew rate between the last
crossing of Vil(dc)max and the first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal slew rate line
between shaded ‘dc to ac region’, use nominal slew rate for derating value (see Fig a.) If the actual signal is later than the nominal
slew rate line anywhere between shaded ‘dc to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc
level is used for derating value (see Fig b.)
crossing of Vref. Hold (tIH & tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
Vih(dc)min and the first crossing of Vref. If the actual signal is always later than the nominal slew rate line between shaded ‘dc to
Vref region’, use nominal slew rate for derating value (see Fig a.) If the actual signal is earlier than the nominal slew rate line any-
where between shaded ‘dc to Vref region’, the slew rate of a tangent line to the actual signal from the dc level to Vref level is used
for derating value (see Fig b.)Input waveform timing is referenced to the input signal crossing through the V
device under test.
V
V
V
V
SYMBOL
V
V
TOPER
IH
IH
IH
IL
IL
IL
(dc)
(dc)
(ac)
(dc)
(dc)
(ac)
dc input logic high
dc input logic high
dc input logic low
dc input logic low
ac input logic high
ac input logic low
Input reference voltage
Input signal maximum peak to peak swing
Input signal minimum slew rate
Parameter
Parameter
Parameter
Operating Temperature
Condition
PARAMETER
V
V
V
REF
REF
REF
- 0.3
- 0.3
Min.
Min.
Min.
+ 0.125
+ 0.125
+ 0.250
-
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V
V
V
0.5 * V
1.0
1.0
V
V
REF
REF
REF
DDQ
DDQ
Value
Max.
Max.
Max.
- 0.125
- 0.125
- 0.250
-
DDQ
+ 0.3
+ 0.3
RATING
0 to 95
V
V
V/ns
Units
Units
Units
Units
V
V
V
V
V
V
1
1
2, 3
Notes
Notes
Notes
Notes
Rev. 0.91 (Sep. 2003)
DDR2 SDRAM
UNITS
°C
REF
Preliminary
level applied to the
NOTES
1, 2