k4t51043qb-gce6 Samsung Semiconductor, Inc., k4t51043qb-gce6 Datasheet - Page 35

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k4t51043qb-gce6

Manufacturer Part Number
k4t51043qb-gce6
Description
512mb B-die Ddr2 Sdram
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
512Mb B-die DDR2 SDRAM
resisor to insure proper operation.
5. AC timings are for linear signal transitions. See System Derating for other signal transitions.
6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They
7. All voltages referenced to VSS.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal refer-
ence/supply voltage levels, but the related specifications and device operation are guaranteed for the full volt-
age range specified.
Specific Notes for dedicated AC parameters
9. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be
used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit
timing where a lower power value is defined by each vendor data sheet.
10. AL = Additive Latency
11. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and
tRAS(min) have been satisfied.
may be guaranteed by device design or tester correlation.
CK/CK
DQS/DQS
DQ
DQS/
DQS
DQ
DM
CK
CK
DQS
DQS
t
CH
t
t
RPRE
DQS
DQS
WPRE
Figure YY-- Data output (read) timing
V
V
IH
IL
(ac)
(ac)
t
DMin
DS
t
t
CL
DQSQmax
D
Figure -- Data input (write) timing
t
DQSH
Page 35 of 38
V
V
IH
IL
(ac)
(ac)
DMin
t
t
QH
DS
D
Q
t
DQSL
DMin
Q
D
t
DH
V
V
IH
IL
(dc)
(dc)
t
DQSQmax
DMin
Q
D
t
DH
V
V
IH
IL
t
(dc)
WPST
(dc)
t
t
RPST
QH
Q
Rev. 0.91 (Sep. 2003)
DDR2 SDRAM
Preliminary

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