k4t51043qb-gce6 Samsung Semiconductor, Inc., k4t51043qb-gce6 Datasheet - Page 30

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k4t51043qb-gce6

Manufacturer Part Number
k4t51043qb-gce6
Description
512mb B-die Ddr2 Sdram
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
512Mb B-die DDR2 SDRAM
For purposes of IDD testing, the following parameters are to be utilized
Detailed IDD7
The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the specification.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect
IDD7: Operating Current: All Bank Interleave Read operation
All banks are being interleaved at minimum t RC(IDD) without violating t RRD(IDD) using a burst length of 4. Control and address bus
inputs are STABLE during DESELECTs. IOUT = 0mA
Timing Patterns for 4 bank devices x4/ x8/ x16
-DDR2-400 3/3/3
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D D
-DDR2-533 4/4/4
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
-DDR2-667 5/5/5
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D
t RFC(IDD)-512Mb
t RRD(IDD)-x4/x8
t RRD(IDD)-x16
t RASmin(IDD)
Parameter
t RCD(IDD)
t RC(IDD)
t CK(IDD)
t RP(IDD)
CL(IDD)
DDR2-667
5-5-5
105
7.5
15
55
10
40
15
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5
3
DDR2-533
4-4-4
3.75
105
7.5
15
55
10
40
15
4
DDR2-400
3-3-3
105
7.5
15
55
10
40
15
3
5
Units
tCK
ns
ns
ns
ns
ns
ns
ns
ns
Rev. 0.91 (Sep. 2003)
DDR2 SDRAM
Preliminary

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