k4h560838c Samsung Semiconductor, Inc., k4h560838c Datasheet - Page 19

• Manufacturer Part Number: k4h560838c
• Description: Ddr Sdram Specification Version 0.6
• Manufacturer: Samsung Semiconductor, Inc.

256Mb C-die(x4/8) DDR SDRAM
is initiated by activating RAS, CS, CAS, and deasserting WE at the same clock sampling(rising) edge as
described in the command truth table. The length of the burst and the CAS latency time will be determined by
the values programmed during the MRS command.
mand is initiated by activating RAS, CS, CAS, and WE at the same clock sampling(rising) edge as described in
the command truth table. The length of the burst will be determined by the values programmed during the
MRS command.
edge of the clock(CK). The DDR SDRAM has four independent banks, so two Bank Select addresses(BA0,
BA1) are required. The Bank Activation command must be applied before any Read or Write operation is exe-
cuted. The delay from the Bank Activation command to the first read or write command must meet or exceed
the minimum of RAS to CAS delay time(tRCD min). Once a bank has been activated, it must be precharged
before another Bank Activation command can be applied to the same bank. The minimum time interval
between interleaved Bank Activation commands(Bank A to Bank B and vice versa) is the Bank to Bank delay
time(tRRD min).
3.2.5 Row Active
3.2.6 Read Bank
3.2.7 Write Bank
The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising
This command is used after the row activate command to initiate the burst read of data. The read command
This command is used after the row activate command to initiate the burst write of data. The write com-
Bank Activation Command Cycle
Command
Address
CK
CK
Row Addr.
Activate
Bank A
Bank A
0
RAS-CAS delay(
Figure 8. Bank activation command cycle timing
NOP
1
t
RCD
Precharge
Col. Addr.
with Auto
)
Write A
Bank A
( CAS Latency = 2)
2
- 19 -
ROW Cycle Time(
t
RC
)
Row Addr.
Activate
Bank B
Bank B
Tn
RAS-RAS delay time(
REV. 0.7 Jan. 31. 2002
NOP
Tn+1
Row. Addr.
t
Activate
Bank A
Bank A
RRD
Tn+2
)
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