k4h560838c Samsung Semiconductor, Inc., k4h560838c Datasheet - Page 25

• Manufacturer Part Number: k4h560838c
• Description: Ddr Sdram Specification Version 0.6
• Manufacturer: Samsung Semiconductor, Inc.

256Mb C-die(x4/8) DDR SDRAM
3.3.7 Write Interrupted by a Read & DM
state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention.
When the read command is registered, any residual data from the burst write cycle must be masked by DM.
The delay from the last data to read command (tCDLR) is required to avoid the data contention DRAM inside.
Data that are presented on the DQ pins before the read command is initiated will actually be written to the
memory. Read command interrupting write can not be issued at the next clock edge of that of write command.
The following function established how a Read command may interrupt a Write burst and which input data is
not written into the memory.
1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock
2. For Read commands interrupting a Write burst, the DM pin must be used to mask the input data words
3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip
4. If input Write data is masked by the Read command, the DQS input is ignored by the DDR SDRAM.
5. Refer to "3.3.2 Burst write operation"
A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance
CAS Latency=2
CAS Latency=2
cycles. The case where the Write to Read delay is 1 clock cycle is disallowed
(i.e., the memory controller) in time to allow the buses to turn around before the DDR SDRAM drives them
during a read operation.
whcich immediately precede the interrupting Read operation and the input data word which immediately
follows the interrupting Read operation
< Burst Length=8, CAS Latency=2 >
Command
D Q S
D Q s
DQS
D Q s
CK
CK
DM
NOP
0
Figure 15. Write interrupted by a read and DM timing
t
WPRES*
t
WRITE
WPRES*
5
t
DQSSmin
1
t
DQSSmax
5
Din 0
NOP
Din 0
Din 1
2
- 25 -
Din 1
Din 2
NOP
Din 2
Din 3
3
Din 3
Din 4
NOP
Din 4
Din 5
4
t
t
WTR
WTR
Din 5
Din 6
READ
Din 6
Din 7
REV. 0.7 Jan. 31. 2002
5
Din 7
NOP
6
NOP
Dout 0 Dout 1 Dout 2
Dout 0 Dout 1 Dout 2 Do
7
NOP
8
Do