k4h560838c Samsung Semiconductor, Inc., k4h560838c Datasheet - Page 31

• Manufacturer Part Number: k4h560838c
• Description: Ddr Sdram Specification Version 0.6
• Manufacturer: Samsung Semiconductor, Inc.

256Mb C-die(x4/8) DDR SDRAM
3.3.13 Auto Refresh & Self Refresh
Auto Refresh
ing edge of the clock(CK). All banks must be precharged and idle for tRP(min) before the auto refresh com-
mand is applied. No control of the external address pins is required once this cycle has started because of the
internal address counter. When the refresh cycle has completed, all banks will be in the idle state. A delay
between the auto refresh command and the next activate command or subsequent auto refresh command
must be greater than or equal to the tRFC(min).
CKE
Self Refresh
edge of the clock(CK). Once the self refresh command is initiated, CKE must be held low to keep the device in
self refresh mode. During the self refresh operation, all inputs except CKE are ignored. The clock is internally
disabled during self refresh operation to reduce power consumption. The self refresh is exited by supplying
stable clock input before returning CKE high, asserting deselect or NOP command and then asserting CKE
high for longer than tXSR for locking of DLL.
1. Exit self refresh to bank active command, a write command can be applied as far as tRCD is satisfied after
2. Exit self refresh to read command
Command
Command
An auto refresh command is issued by having CS, RAS and CAS held low with CKE and WE high at the ris-
A self refresh command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising
any bank active command.
= High
CK
CK
CKE
CK
CK
Refresh
PRE
Self
t
RP
Refresh
Auto
Figure 21. Auto refresh timing
Figure 22. Self refresh timing
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t
RFC
t
XSNR
REV. 0.7 Jan. 31. 2002
* 1
t
XSRD*
Active
2
CMD
Read