mt16htf25664ay-80e Micron Semiconductor Products, mt16htf25664ay-80e Datasheet - Page 14

• Manufacturer Part Number: mt16htf25664ay-80e
• Description: 512mb, 1gb, 2gb, 4gb X64, Dr 240-pin Ddr2 Sdram Udimm
• Manufacturer: Micron Semiconductor Products

Table 15:
PDF: 09005aef80f09084/Source: 09005aef80f09068
HTF16C64_128_256x64A.fm - Rev. F 8/07 EN
Parameter/Condition
Operating one bank active-precharge current:
t
inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
CL = CL (I
t
inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
Other control and address bus inputs are stable; Data bus inputs are floating
Precharge quiet standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are
floating
Precharge standby current: All device banks idle;
HIGH; Other control and address bus inputs are switching; Data bus inputs are
switching
Active power-down current: All device banks open;
t
are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
commands; Other control and address bus inputs are switching; Data bus inputs are
switching
Operating burst write current: All device banks open; Continuous burst writes;
BL = 4, CL = CL (I
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst reads;
I
t
are switching; Data bus inputs are switching
Burst refresh current:
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address
bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus
inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving reads;
I
t
valid commands; Address bus inputs are stable during deselects; Data bus inputs are
switching
OUT
OUT
RAS =
RCD =
CK =
RAS =
RP =
RC =
= 0mA; BL = 4, CL = CL (I
= 0mA; BL = 4, CL = CL (I
t
t
t
RP (I
RC (I
CK (I
t
t
t
RAS MIN (I
RAS MAX (I
RCD (I
DD
DD
DD
DD
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
),
DDR2 I
Values are shown for the MT47H256M8 DDR2 SDRAM only and are computed from values specified in the
2Gb (256 Meg x 8) component data sheet
); CKE is LOW; Other control and address bus inputs
DD
t
RRD =
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus
DD
Notes:
), AL = 0;
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus
t
),
CK =
DD
t
RRD (I
t
RP =
t
CK =
Specifications and Conditions – 4GB
t
CK (I
1. Value calculated as one module rank in this operating condition; all other module ranks in
2. Value calculated reflects all module ranks in this operating condition.
t
DD
DD
CK =
t
DD
RP (I
t
CK (I
I
), AL = 0;
), AL =
DD
),
DD
t
2P (CKE LOW) mode.
t
DD
RCD =
),
CK (I
512MB, 1GB, 2GB, 4GB (x64, DR) 240-Pin DDR2 SDRAM UDIMM
DD
t
); CKE is HIGH, S# is HIGH between valid
RC =
); REFRESH command at every
t
RCD (I
DD
t
t
CK =
RCD (I
),
t
RC (I
t
RAS =
DD
DD
t
CK (I
) - 1 ×
DD
DD
4W
t
),
CK =
); CKE is HIGH, S# is HIGH between
t
t
RAS MAX (I
t
t
DD
CK =
CK =
RAS =
t
),
CK (I
t
CK (I
t
t
RAS =
t
OUT
CK =
t
CK (I
CK (I
t
t
DD
CK =
14
RAS MIN (I
DD
);
= 0mA; BL = 4,
DD
t
DD
DD
),
t
t
CK (I
RAS MAX (I
CK =
t
),
CK (I
),
); CKE is HIGH, S# is
t
t
RC =
RP =
DD
t
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
RFC (I
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
CK (I
DD
); CKE is LOW;
); CKE is
t
),
t
RC (I
RP (I
DD
DD
DD
)
),
DD
),
DD
),
);
Symbol
I
I
I
I
I
I
I
DD
DD
DD
DD
I
I
DD
DD
DD
I
I
I
Electrical Specifications
DD
DD
DD
DD
DD
4W
2Q
2N
3N
2P
3P
4R
0
1
5
6
7
1
1
2
2
1
2
2
1
2
2
2
1
©2003 Micron Technology, Inc. All rights reserved.
1,216
1,256
1,416
4,480
2,776
-667
856
128
880
960
640
160
880
128
1,096
1,256
4,160
2,416
-53E
776
896
128
720
800
560
160
720
128
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA