k9f1g08r0a Samsung Semiconductor, Inc., k9f1g08r0a Datasheet

Page 1

... K9F1G08R0A K9K2G08U1A K9F1G08U0A Document Title 128M x 8 Bit / 256M x 8 Bit Revision History Revision No History 0.0 1. Initial issue 0.1 1. The tADL(Address to Data Loading Time) is added. - tADL Minimum 100ns (Page 11, 23~26) - tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle at program operation. ...

Page 2

... PRODUCT LIST Part Number K9F1G08R0A K9F1G08U0A-Y,P K9F1G08U0A-V,F K9K2G08U1A-I FEATURES Voltage Supply -1.8V device(K9F1G08R0A): 1.65V~1.95V -3.3V device(K9F1G08U0A): 2.7 V ~3.6 V Organization - Memory Cell Array : (128M + 4,096K)bit x 8bit - Data Register : (2K + 64)bit x8bit - Cache Register : (2K + 64)bit x8bit Automatic Program and Erase - Page Program : (2K + 64)Byte - Block Erase : (128K + 4K)Byte ...

Page 3

... K9F1G08R0A K9K2G08U1A K9F1G08U0A PIN CONFIGURATION (TSOP1) K9F1G08X0A-YCB0,PCB0/YIB0,PIB0 X8 N.C 1 N.C 2 N.C 3 N.C 4 N.C 5 N N.C 10 N.C 11 Vcc 12 Vss 13 N.C 14 N.C 15 CLE 16 ALE N.C 20 N.C 21 N.C 22 N.C 23 N.C 24 PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE( TSOP1 - 1220AF #1 #24 0~8 0.45~0.75 0.018~0.030 48 47 ...

Page 4

... K9F1G08R0A K9K2G08U1A K9F1G08U0A PIN CONFIGURATION (WSOP1) N.C 1 N.C 2 DNU 3 N.C 4 N.C 5 N DNU 10 N.C 11 Vcc 12 Vss 13 N.C 14 DNU 15 CLE 16 ALE N.C 20 N.C 21 DNU 22 N.C 23 N.C 24 PACKAGE DIMENSIONS 48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE ( WSOP1 - 1217F #1 #24 ...

Page 5

... K9F1G08R0A K9K2G08U1A K9F1G08U0A PIN CONFIGURATION (ULGA /CE1 4 3 CLE1 PACKAGE DIMENSIONS 52-ULGA (measured in millimeters) Top View 12.00 0.10 #A1 K9K2G08U1A-ICB0/IIB0 /RE1 /RB2 IO7-2 IO6-2 NC IO5-2 Vcc /RE2 Vss IO7-1 IO5-1 Vcc ...

Page 6

... K9F1G08R0A K9K2G08U1A K9F1G08U0A PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS I/O ~ I/O The I/O pins are used to input command, address and data, and to output data during read operations. The pins float to high-z when the chip is deselected or when the outputs are disabled. COMMAND LATCH ENABLE CLE The CLE input controls the activating path for commands sent to the command register ...

Page 7

... K9F1G08R0A K9K2G08U1A K9F1G08U0A Figure 1-1. K9F1G08X0A Functional Block Diagram X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High Voltage WE Generator CLE ALE PRE Figure 2-1. K9F1G08X0A Array Organization ...

Page 8

... K9F1G08R0A K9K2G08U1A K9F1G08U0A Product Introduction The K9F1G08X0A is a 1056Mbit(1,107,296,256 bit) memory organized as 65,536 rows(pages) by 2112x8 columns. Spare 64 col- umns are located from column address of 2048~2111. A 2112-byte data register and a 2112-byte cache register are serially con- nected to each other. Those serially connected registers are connected to memory cell arrays for accommodating data transfer between the I/O buffers and memory cells during page read and page program operations ...

Page 9

... Input High Voltage V IH* Input Low Voltage, All inputs V IL* K9F1G08R0A :I Output High Voltage Level V OH K9F1G08U0A :I Output Low Voltage Level K9F1G08R0A : K9F1G08U0A :I K9F1G08R0A :V Output Low Current(R/B) I (R/B) OL K9F1G08U0A :V NOTE : V can undershoot to -0.4V and V can overshoot Symbol 1.8V DEVICE V -0 2.45 IN/OUT V -0 ...

Page 10

... Each K9F1G08U0A chip in the K9K2G08U1A has Maximum 20 invalid blocks TEST CONDITION (K9F1G08X0A-XCB0 :TA K9F1G08X0A-XIB0:TA=- K9F1G08R0A : Vcc=1.65V~1.95V, K9F1G08U0A : Vcc=2.7V~3.6V unless otherwise noted) Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load ...

Page 11

... Output Hi Low RE High to WE Low WE High to RE Low Device Resetting Time (Read/Program/Erase) NOTE reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us. 2. For cache program operation, the whole AC Charcateristics must be same as that of K9F1G08R0A. Min K9F1G08R0A K9F1G08U0A *1 25 ...

Page 12

... K9F1G08R0A K9K2G08U1A K9F1G08U0A NAND Flash Technical Notes Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block( called as the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics ...

Page 13

... K9F1G08R0A K9K2G08U1A K9F1G08U0A NAND Flash Technical Notes Error in write or read operation Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the block failure rate.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done ...

Page 14

... K9F1G08R0A K9K2G08U1A K9F1G08U0A NAND Flash Technical Notes Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Yes * No Erase Error I Yes Erase Completed : If erase operation results in an error, map out * the failing block and replace it with another block. ...

Page 15

... K9F1G08R0A K9K2G08U1A K9F1G08U0A NAND Flash Technical Notes Addressing for program operation Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most sig- nificant bit) pages of the block. Random page address programming is prohibited. (64) ...

Page 16

... K9F1G08R0A K9K2G08U1A K9F1G08U0A System Interface Using CE don’t-care. For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2112byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and serial access would provide significant savings in power consumption ...

Page 17

... K9F1G08R0A K9K2G08U1A K9F1G08U0A NOTE I/O Device I/Ox K9F1G08X0A I I/O 7 Command Latch Cycle CLE ...

Page 18

... K9F1G08R0A K9K2G08U1A K9F1G08U0A Input Data Latch Cycle CLE ALS ALE ...

Page 19

... K9F1G08R0A K9K2G08U1A K9F1G08U0A Status Read Cycle CLE I/Ox t CLR t CLS t CLH ...

Page 20

... K9F1G08R0A K9K2G08U1A K9F1G08U0A Read Operation CLE ALE I/Ox 00h Col. Add1 Col. Add2 ...

Page 21

... K9F1G08R0A K9K2G08U1A K9F1G08U0A FLASH MEMORY ...

Page 22

... K9F1G08R0A K9K2G08U1A K9F1G08U0A Page Program Operation CLE ALE I/ Col. Add2 80h Co.l Add1 SerialData Column Address ...

Page 23

... K9F1G08R0A K9K2G08U1A K9F1G08U0A ...

Page 24

... K9F1G08R0A K9K2G08U1A K9F1G08U0A ...

Page 25

... K9F1G08R0A K9K2G08U1A K9F1G08U0A FLASH MEMORY ...

Page 26

... K9F1G08R0A K9K2G08U1A K9F1G08U0A BLOCK ERASE OPERATION CLE ALE I/ 60h Row Add1 Row Add2 Row Address R/B Auto Block Erase Erase Command Setup Command ...

Page 27

... K9F1G08R0A K9K2G08U1A K9F1G08U0A Read ID Operation CLE CE WE ALE RE I/Ox 90h Read ID Command Address. 1cycle Device K9F1G08R0A K9F1G08U0A K9K2G08U1A ID Defintition Table Access command = 90H Description 1 st Byte Maker Code 2 nd Byte Device Code 3 rd Byte Don’t care Page Size, Block Size, Spare Size, Organization,Serial access minimum ...

Page 28

... K9F1G08R0A K9K2G08U1A K9F1G08U0A 4th ID Data ITEM Description 1KB Page Size 2KB (w/o redundant area ) Reserved Reserved 64KB Block Size 128KB (w/o redundant area ) 256KB Reserved Redundant Area Size 8 ( byte/512byte Organization x16 50ns/30ns 25ns Serial Access minimum Reserved Reserved FLASH MEMORY I/O7 I/O6 I/O5 I/O4 I/ ...

Page 29

... K9F1G08R0A K9K2G08U1A K9F1G08U0A Device Operation PAGE READ Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data within the selected page are transferred to the data registers in less than 25 s(t this data transfer(tR) by analyzing the output of R/B pin ...

Page 30

... K9F1G08R0A K9K2G08U1A K9F1G08U0A Figure 7. Random Data Output In a Page R/B RE Address I/Ox 00h 30h 4Cycles Col Add1,2 & Row Add1,2 PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a word or consecutive bytes up to 2112 single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for main array(1time/512byte) and 4 times for spare array(1time/16byte) ...

Page 31

... K9F1G08R0A K9K2G08U1A K9F1G08U0A Figure 9. Random Data Input In a Page R/B I/Ox Address & Data Input 80h Col Add1,2 & Row Add1,2 Data Cache Program Cache Program is an extension of Page Program, which is executed with 2112byte data registers, and is available only within a block. Since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed into memory cell ...

Page 32

... K9F1G08R0A K9K2G08U1A K9F1G08U0A NOTE : Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after comple- tion of the previous cycle, which can be expressed as the following formula ...

Page 33

... K9F1G08R0A K9K2G08U1A K9F1G08U0A BLOCK ERASE The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup com- mand(60h). Only address valid while address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions ...

Page 34

... AR t WHR t REA Device ECh Code* Maker code Device code Device Device Code*(2nd Cycle) K9F1G08R0A A1h K9F1G08U0A F1h K9K2G08U1A Same as each K9F1G08U0A RST After Power-up 00h command is latched 34 FLASH MEMORY XXh 4th Cyc.* 4th Cycle* ...

Page 35

... K9F1G08R0A K9K2G08U1A K9F1G08U0A READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis- ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...

Page 36

... K9F1G08R0A K9K2G08U1A K9F1G08U0A Data Protection & Power up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device), 2V(3.3V device). WP pin provides hardware protection and is recommended to be kept at V during power-up and power-down. A recovery time of minimum required before internal circuit IL gets ready for any command sequences as shown in Figure 17 ...

Page 37

... K9F1G08R0A K9K2G08U1A K9F1G08U0A Extended Data Out Mode For the EDO mode, the device should hold the data on the system memory bus until the beginning of the next cycle, so that controller could fetch the data at the falling edge. However NAND flash dosen’t support the EDO mode exactly. ...