k9f1g08r0a Samsung Semiconductor, Inc., k9f1g08r0a Datasheet - Page 34

• Manufacturer Part Number: k9f1g08r0a
• Description: 128m X 8 Bit / 256m X 8 Bit Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

K9F1G08R0A
K9F1G08U0A
Table3. Device Status
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Four read cycles sequentially output the manufacturer code(ECh), and the device code and XXh, 4th cycle ID, respectively. The
command register remains in Read ID mode until further commands are issued to it. Figure 14 shows the operation sequence.
Figure 14. Read ID Operation
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 3 for device status after reset operation.If the device is
already in reset state a new reset command will be accepted by the command register. The R/B pin transitions to low for tRST after
the Reset command is written. Refer to Figure 15 below.
Figure 15. RESET Operation
R/B
I/O
CLE
CE
WE
ALE
RE
I/O
X
X
Operation Mode
90h
FFh
K9K2G08U1A
x x x x x x x
x x x x x x x
x x x x x x x
x x x x x x x
x x x x x x x
Address. 1cycle
00h
t
CLR
K9K2G08U1A
K9F1G08R0A
K9F1G08U0A
x x x x x x x
x x x x x x x
x x x x x x x
x x x x x x x
x x x x x x x
00h command is latched
Device
t
WHR
After Power-up
t
AR
t
CEA
t
REA
t
RST
Maker code
Device Code*(2nd Cycle)
34
ECh
Same as each K9F1G08U0A in it
A1h
F1h
Device code
Device
Code*
Waiting for next command
XXh
FLASH MEMORY
4th Cycle*
After Reset
15h
15h
4th Cyc.*