hx6256 Honeywell International's Solid State Electronics Center (SSEC), hx6256 Datasheet - Page 6

• Manufacturer Part Number: hx6256
• Description: 32k X 8 Static Ram Solid State Electronics Center
• Manufacturer: Honeywell International's Solid State Electronics Center (SSEC)

HX6256
READ CYCLE AC TIMING CHARACTERISTICS (1)
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V,
(2) Typical operating conditions: VDD=5.0 V, TA=25°C, pre-radiation.
(3) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55 to 125°C, post total dose at 25°C.
(4) Chip Enable (CE) pin not available on 28-lead FP or DIP.
6
TAVAVR
TAVQV
TAXQX
TSLQV
TSLQX
TSHQZ
TEHQV
TEHQX
TELQZ
TGLQV
TGLQX
TGHQZ
input and output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading C
or equivalent capacitive output loading C
(typical).
Symbol
Address Read Cycle Time
Address Access Time
Address Change to Output Invalid Time
Chip Select Access Time
Chip Select Output Enable Time
Chip Select Output Disable Time
Chip Select Access Time (4)
Chip Select Output Enable Time (4)
Chip Select Output Disable Time (4)
Output Enable Access Time
Output Enable Output Enable Time
Output Enable Output Disable Time
Parameter
L
=5 pF for TSHQZ, TELQZ TGHQZ. For C
Typical
(2)
17
14
17
10
17
10
9
4
4
4
4
2
L
>50 pF, derate access times by 0.02 ns/pF
Min
Worst Case (3)
25
3
5
5
0
www.honeywell.com/radhard
Max
25
10
25
10
25
9
9
L
>50 pF,
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns