lamxo256e Lattice Semiconductor Corp., lamxo256e Datasheet - Page 13

• Manufacturer Part Number: lamxo256e
• Description: La-machxo Automotive Family Data Sheet
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Table 2-5. PLL Signal Descriptions
For more information on the PLL, please see details of additional technical documentation at the end of this data
sheet.
sysMEM Memory
The LA-MachXO1200 and LA-MachXO2280 devices contain sysMEM Embedded Block RAMs (EBRs). The EBR
consists of a 9-Kbit RAM, with dedicated input and output registers.
sysMEM Memory Block
The sysMEM block can implement single port, dual port, pseudo dual port, or FIFO memories. Each block can be
used in a variety of depths and widths as shown in Table 2-6.
Table 2-6. sysMEM Block Configurations
CLKI
CLKFB
RST
CLKOS
CLKOP
CLKOK
LOCK
CLKINTFB
DDAMODE
DDAIZR
DDAILAG
DDAIDEL[2:0]
Signal
I/O
O
O
O
O
O
I
I
I
I
I
I
I
Clock input from external pin or routing
PLL feedback input from PLL output, clock net, routing/external pin or internal feedback from
CLKINTFB port
“1” to reset the input clock divider
PLL output clock to clock tree (phase shifted/duty cycle changed)
PLL output clock to clock tree (No phase shift)
PLL output to clock tree through secondary clock divider
“1” indicates PLL LOCK to CLKI
Internal feedback source, CLKOP divider output before CLOCKTREE
Dynamic Delay Enable. “1”: Pin control (dynamic), “0”: Fuse Control (static)
Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on
Dynamic Delay Lag/Lead. “1”: Lag, “0”: Lead
Dynamic Delay Input
Single Port
True Dual Port
Pseudo Dual Port
FIFO
Memory Mode
2-10
LA-MachXO Automotive Family Data Sheet
Configurations
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
256 x 36
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
256 x 36
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
256 x 36
512 x 18
Description
Architecture