cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 256

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cn8237

Manufacturer Part Number
cn8237
Description
Atm Oc-12 Servicesar Plus With Xbr Traffic Management
Manufacturer
Mindspeed Technologies
Datasheet

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11.0 PHY Interface
11.2 Microprocessor Interface to PHY Device(s)
Figure 11-3. CN8237/RS825x Read/Write Functional Timing (Normal Mode)
11-4
PADDR[12:0]
PDATA[7:0]
PWAIT*
PWNR
PCLK
PCS*
PDS*
PAS*
tA
1, 2 Read Cycle
edge of PCLK) the RS825x samples PCS*, PAS*, and PWNR low, indicating a
read cycle. By the next rising edge of PCLK at cycle two, the data is output by the
RS825x to be latched by the CN8237. The same procedure occurs for a write
except that at cycle four, PWNR is sampled high. The RS825x then latches the
data to the appropriate internal register on the next PCLK rising edge at cycle
five.
1
Figure 11-3
Read Address
Read Data
tD
Mindspeed Technologies
2
shows a read and write RS825x access. At cycle one (the rising
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
3
tA
4, 5 Write Cycle
Write Address
Write Data
4
tD
5
28237-DSH-001-C
6
CN8237
8237_092

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