cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 328

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

14.0 CN8237 Registers
14.7 PCI Bus Interface Registers
Table 14-7. PCI Special Status Register (0x40) (2 of 2)
14-38
NOTE(S):
(1)
15–12
7–0
Bit
11
10
Can be loaded from EEPROM.
9
8
Field
Size
4
1
1
1
1
8
PLL_MUL
INTF_DIS
INT_FAIL
MERROR
MRD
Reserved
(1)
Name
Mindspeed Technologies
PLL_MUL, PLL Multiplier value. Only 0x4 through 0xa (multiplier values of
4 through 10) are valid.
Upon an active reset, HRST* = 0, this register is set to 0x4 if HM66EN = 1
and 0x8 if HM66EN = 0.
Master Interface Disabled. If the M_EN bit in the COMMAND field is a logic
low, any attempt by the CN8237 to perform a DMA transaction to the PCI
bus will result in an error. INTF_DIS and MERROR bits set to a logic high.
This bit can be reset by writing a logic high to itself.
Master Interface Failed. Set to a logic high when an internal PCI/DMA
synchronization error has occurred. The MERROR bit is also set to a logic
high. This bit can be reset by writing a logic high to itself.
Memory Error. Indicates that the PCI bus master has encountered a fatal
error and therefore has halted operation. Set when either RTA, RMA, DPR,
INTF_DIS, or INT_FAIL errors occur. This bit can be reset by writing a logic
high to itself.
Error on Master Read/Write. If a logic high, indicates that the errored
transaction was a read and the address of the read is located in the
MASTER_READ_ADDR field. If a logic low, indicates the errored
transaction was a write and the corresponding address is located in the
MASTER_WRITE_ADDR field.
Set to 0x00.
0000 = 16
0001 = 17
0010 = 2
0011 = 3
0100 = 4
0101 = 5
0110 = 6
0111 = 7
1000 = 8
1001 = 9
1010 = 10
1011 = 11
1100 = 12
1101 = 13
1110 = 14
1111 = 15
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
™
Description
28237-DSH-001-C
CN8237