cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 259

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
11.4.1 Strobe Mode
28237-DSH-001-C
11.4.1.1 Wait Mode
NOTE:
To activate the strobe mode, set PHY_STROBE_IO (bit 29 of the CONFIG1
register) high. In strobe mode, PAS*, PDS*, and PWNR are redefined to be an
active high address strobe, an active low read enable strobe, and an active low
write enable strobe, respectively. This provides a glueless interface to most PHY
devices using standard RAM-type interface signals. See the timing diagram in
Section 16.1.4
Wait states can be internally generated by setting PHY_WAIT (bits 27 and 28 of
the CONFIG1 register) to 1, 2, or 3, while a setting of zero disables internal wait
state generation. When set to other than zero, the interface state machine
automatically inserts the appropriate number of wait states during the data phase
of the access or during the read/write strobe time if in strobe mode. The PWAIT*
input remains enabled and can generate additional externally controlled wait
states.
NOTE:
The three lower address bits of the PCI address bus are not used by the
PHY block. Because a byte-only interface is supported and the PCI
interface is a full 64-bit, quad-word interface, the upper bits of all accesses
are ignored on writes and return zeros on reads. The addressing is shifted
to accommodate this as is standard fashion in this type of interface.
The internally set wait period cannot be shortened by use of the PWAIT*
input.
Mindspeed Technologies
for more information.
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11.4 Interface Control
11.0 PHY Interface
11-7