M25P05-AVDW6G NUMONYX [Numonyx B.V], M25P05-AVDW6G Datasheet - Page 24

• Manufacturer Part Number: M25P05-AVDW6G
• Description: 512 Kbit, serial Flash memory, 50 MHz SPI bus interface
• Manufacturer: NUMONYX [Numonyx B.V]

Instructions
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When the status register write disable (SRWD) bit of the status register is set to ‘1’, two
cases need to be considered, depending on the state of Write Protect (W):
Regardless of the order of the two events, the hardware protected mode (HPM) can be
entered:
The only way to exit the hardware protected mode (HPM) once entered is to pull Write
Protect (W) High.
If Write Protect (W) is permanently tied High, the hardware protected mode (HPM) can
never be activated, and only the software protected mode (SPM), using the block protect
(BP1, BP0) bits of the status register, can be used.
Figure 11. Write status register (WRSR) instruction sequence
If Write Protect (W) is driven High, it is possible to write to the status register provided
that the write enable latch (WEL) bit has previously been set by a write enable (WREN)
instruction
If Write Protect (W) is driven Low, it is not possible to write to the status register even if
the write enable latch (WEL) bit has previously been set by a write enable (WREN)
instruction (attempts to write to the status register are rejected, and are not accepted
for execution). As a consequence, all the data bytes in the memory area that are
software protected (SPM) by the block protect (BP1, BP0) bits of the status register, are
also hardware protected against data modification.
by setting the status register write disable (SRWD) bit after driving Write Protect (W)
Low
or by driving Write Protect (W) Low after setting the status register write disable
(SRWD) bit.
S
C
D
Q
0
1
High Impedance
2
Instruction
3
4
5
6
7
MSB
7
8
6
9 10 11 12 13 14 15
5
register in
4
Status
3
2
1
0
AI02282D
M25P05-A