M25P05-AVDW6G NUMONYX [Numonyx B.V], M25P05-AVDW6G Datasheet - Page 26

• Manufacturer Part Number: M25P05-AVDW6G
• Description: 512 Kbit, serial Flash memory, 50 MHz SPI bus interface
• Manufacturer: NUMONYX [Numonyx B.V]

Instructions
6.6
26/52
Read data bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the read
data bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on Serial Data output (Q), each bit being shifted out, at a maximum
frequency f
The instruction sequence is shown in
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single read data bytes (READ) instruction.
There is no address roll-over; when the highest address (0FFFFh) is reached, the
instruction should be terminated.
The read data bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any read data bytes (READ)
instruction, while an erase, program or write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
Figure 12. Read data bytes (READ) instruction sequence and data-out sequence
1. Address bits A23 to A16 must be set to 00h.
S
C
D
Q
R
0
, during the falling edge of Serial Clock (C).
1
High Impedance
2
Instruction
3
4
5
6
7
MSB
23
8
22 21
9 10
Figure
24-bit address
12.
3
28 29 30 31 32 33 34 35
2
1
0
MSB
7
6
5
Data out 1
4
3
36 37 38
2
1
39
0
7
M25P05-A
Data out 2
AI03748D