eds1232aase Elpida Memory, Inc., eds1232aase Datasheet - Page 26

• Manufacturer Part Number: eds1232aase
• Description: 128m Bits Sdram
• Manufacturer: Elpida Memory, Inc.

Power-up sequence
Power-up sequence
The SDRAM should be goes on the following sequence with power up.
The CLK, CKE, /CS, DQM and DQ pins keep low till power stabilizes.
The CLK pin is stabilized within 100 µs after power stabilizes before the following initialization sequence.
The CKE and DQM is driven to high between power stabilizes and the initialization sequence.
This SDRAM has VDD clamp diodes for CLK, CKE, address, /RAS, /CAS, /WE, /CS, DQM and DQ pins. If these
pins go high before power up, the large current flows from these pins to VDD through the diodes.
Initialization sequence
When 200 µs or more has past after the above power-up sequence, all banks must be precharged using the
precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF). Set the mode register
set command (MRS) to initialize the mode register. We recommend that by keeping DQM and CKE to High, the
output buffer becomes High-Z during Initialization sequence, to avoid DQ bus contention on memory system formed
with a number of device.
Data Sheet E0350E31 (Ver. 3.1)
VDD, VDDQ
CKE, DQM
/CS, DQ
CLK
Power up sequence
0 V
Low
Low
Low
Power-up sequence and Initialization sequence
Power stabilize
100 μs
26
Initialization sequence
200 μs
EDS1232AASE