eds1232aase Elpida Memory, Inc., eds1232aase Datasheet - Page 29

• Manufacturer Part Number: eds1232aase
• Description: 128m Bits Sdram
• Manufacturer: Elpida Memory, Inc.

Auto Precharge
Read with auto-precharge
In this operation, since precharge is automatically performed after completing a read operation, a precharge
command need not be executed after each read operation. The command executed for the same bank after the
execution of this command must be the bank active (ACT) command. In addition, an interval defined by lAPR is
required before execution of the next command.
[Clock cycle time]
/CAS latency
3
2
Write with auto-precharge
In this operation, since precharge is automatically performed after completing a burst write or single write operation,
a precharge command need not be executed after each write operation. The command executed for the same bank
after the execution of this command must be the bank active (ACT) command. In addition, an interval of lDAL is
required between the final valid data input and input of next command.
Data Sheet E0350E31 (Ver. 3.1)
CL=2 Command
CL=3 Command
CLK
DQ
DQ
Command
Note: Internal auto-precharge starts at the timing indicated by "
Note: Internal auto-precharge starts at the timing indicated by "
ACT
ACT
And an interval of tRAS (
CLK
DQ
and an interval of tRAS (lRAS) is required between previous active (ACT) command
and internal precharge "
ACT
l
RAS) is required between previous active (ACT) command and internal precharge "
Precharge start cycle
2 cycle before the final data is output
1 cycle before the final data is output
".
lRAS
lRAS
Burst Write (BL = 4)
Burst Read (BL = 4)
lRAS
READA
READA
".
WRITA
in0
29
in1
out0
in2
out1
out0
in3
".
out1
out2
".
lDAL
out3
out2
lAPR
EDS1232AASE
out3
ACT
lAPR
ACT
ACT