sii3114 Silicon image, sii3114 Datasheet
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... SiI3114 PCI to Serial ATA Controller Data Sheet Document # SiI-DS-0103-D Data Sheet ...
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... Maximum Ratings; Corrected inconsistent sentences (minor fixes including mistyping) A2 10/30/03 Updated Section 8.2 Serial ATA Device Initialization Corrected part number on cover page to SiI3114CT176 from SiI3114CT144 A3 02/05/04 Updated the part number on cover page to SiI3114 from SiI3114CT176; Added Part Ordering A4 04/05/05 Number in section 4. Package Drawing; Updated Marking Specification in section 4. Package Drawing B 07/21/06 Corrected inconsistent sentences (minor fixes including mistyping) ...
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... PCI Class Code – Revision ID .............................................................................................................. 28 BIST – Header Type – Latency Timer – Cache Line Size..................................................................... 28 Base Address Register 0....................................................................................................................... 29 Base Address Register 1....................................................................................................................... 29 © 2007 Silicon Image, Inc. Table of Contents iii SiI3114 PCI to Serial ATA Controller Data Sheet SiI-DS-0103-D ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet Base Address Register 2....................................................................................................................... 29 Base Address Register 3....................................................................................................................... 30 Base Address Register 4....................................................................................................................... 30 Base Address Register 5....................................................................................................................... 30 Subsystem ID – Subsystem Vendor ID ................................................................................................. 31 Expansion ROM Base Address ............................................................................................................. 31 Capabilities Pointer ............................................................................................................................... 32 Max Latency – Min Grant – Interrupt Pin – Interrupt Line ..................................................................... 32 Configuration ...
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... Serial ATA SActive ................................................................................................................................. 70 SMisc..................................................................................................................................................... 70 Serial ATA PHY Configuration ............................................................................................................... 71 SIEN ...................................................................................................................................................... 72 SFISCfg ................................................................................................................................................. 73 RxFIS0-RxFIS6 ..................................................................................................................................... 73 Programming Sequences .......................................................................................................................... 74 Recommended Initialization Sequence for the SiI3114...................................................................... 74 Serial ATA Device Initialization .............................................................................................................. 75 Issue ATA Command............................................................................................................................... 76 PIO Mode Read/Write Operation............................................................................................................ 76 Watchdog Timer Operation .................................................................................................................... 77 PIO Mode Read Ahead Operation.......................................................................................................... 78 MDMA/UDMA Read/Write Operation ..................................................................................................... 78 Virtual DMA Read/Write Operation ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet ATA Command Decoding........................................................................................................................... 90 Data Modes .............................................................................................................................................. 90 ATA Commands....................................................................................................................................... 90 Obsolesced Commands ........................................................................................................................ 92 Read/Write Long.................................................................................................................................... 92 Vendor Specific Command Support ..................................................................................................... 93 Silicon Image's Vendor Specific Commands......................................................................................... 93 Vendor Specific, Reserved, Retired and Obsolesced Commands ....................................................... 94 Definitions.............................................................................................................................................. 94 Scheme ................................................................................................................................................. 94 Bridge Device Vendor Specific Commands ......................................................................................... 96 Feature Set/Command Summary ...
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... Figure 1. Address Lines During Configuration Cycle ..................................................................................... 3 Figure 2. Flash Memory Timing ...................................................................................................................... 7 Figure 3. SiI3114 Pin Diagram...................................................................................................................... 13 Figure 4. Package Drawing – 176 TQFP ..................................................................................................... 19 Figure 5. Marking Specification – SiI3114CT176 ......................................................................................... 20 Figure 6. Marking Specification – SiI3114CTU............................................................................................. 20 Figure 7. SiI3114 Block Diagram .................................................................................................................. 21 Figure 8. Auto-Initialization from Flash Timing ............................................................................................. 22 Figure 9. Auto-Initialization from EEPROM Timing....................................................................................... 23 Figure 10. Hot Plug Logic State Diagram ..................................................................................................... 84 © ...
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... Table 18. SiI3114 Internal Register Space – Base Address 1 ...................................................................... 41 Table 19. SiI3114 Internal Register Space – Base Address 2 ...................................................................... 42 Table 20. SiI3114 Internal Register Space – Base Address 3 ...................................................................... 43 Table 21. SiI3114 Internal Register Space – Base Address 4 ...................................................................... 44 Table 22. SiI3114 Internal Register Space – Base Address 5 ...................................................................... 46 Table 23 ...
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... PCI bus, processes them, and transfers data between the host and Serial ATA devices. It can be used to control four independent Serial ATA channels. Each channel has its own Serial ATA bus and will support one Serial ATA device. The SiI3114 supports a 32-bit 66 MHz PCI bus and the Serial ATA Generation 1 transfer rate of 1.5 Gbit/s (150 MB/s). ...
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... This is accomplished with a configuration write cycle. PCI Bus Operations The SiI3114 behaves either as a PCI master or a PCI slave device at any time and switches between these modes as required during device operation PCI slave, the SiI3114 responds to the following PCI bus operations: • ...
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... PCI configuration read cycles. Deviations from the Specification The SiI3114 product has been developed and tested to the specification listed in this document result of testing and customer feedback, we may become aware of deviations to the specification that could affect the component's operation. To ensure awareness of these deviations by anyone considering the use of the SiI3114, we have included an Errata section at the end of this specification. Please ensure that the Errata section is © ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet carefully reviewed also important that you have the most current version of this specification. If there are any questions, please contact Silicon Image, Inc. Electrical Characteristics Device Electrical Characteristics Specifications are for Commercial Temperature range, 0 ...
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... Ref Clk REXT = 4.99k 1% for 100MHz SerDes Ref Clk Condition 20%-80 SerDes Ref Clk = SSC AC modulation, subject to the "Downspread SSC" triangular modulation (30-33KHz) profile per 6.6.4.5 in SATA 1.0 specification 5 SiI3114 PCI to Serial ATA Controller Data Sheet Limits Min Typ Max 400 500 600 500 600 700 550 ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet SATA Interface Transmitter Output Jitter Characteristics Table 5. SATA Interface Transmitter Output Jitter Characteristics Symbol Parameter RJ 5UI later Random Jitter 5UI RJ 250UI later Random 250UI Jitter DJ 5UI later Deterministic 5UI Jitter DJ 250UI later Deterministic 250UI ...
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... FL_CS_N FL_WR_N © 2007 Silicon Image, Inc. Table 8. PCI 66 MHz Timing Specifications CYC FLASH READ TIMING CYC CYC FLASH WRITE TIMING Figure 2. Flash Memory Timing 7 SiI3114 PCI to Serial ATA Controller Data Sheet Limits Unit Min Max 2.0 6.0 ns 2.0 6 ...
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... Pin Definitions SiI3114 Pin Listing This section describes the pins of the SiI3114 PCI-to-Serial ATA host controller. Table 9 provides information on pin numbers, pin names, pin types, drive types where applicable, internal resistors where applicable, and descriptions. Table 10 shows the pin types used in the SiI3114. ...
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... O PU – 70k Flash Memory Chip Select PWR - 1.8V Internal Core Power GND - Ground OD PU – 70k Channel 3 activity LED indicator I/O PU – 70k Flash Memory Data 0 I/O PU – 70k Flash Memory Data 1 9 SiI3114 PCI to Serial ATA Controller Data Sheet SiI-DS-0103-D ...
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... PCI_AD18 126 PCI_AD17 127 PCI_AD16 128 PCI_CBE2 129 PCI_FRAME_N 130 PCI_IRDY_N 131 PCI_PERR_N 132 VDDO SiI-DS-0103-D Table 9. SiI3114 Pin Listing (continued) Type Internal Description Resistor I/O PU – 70k Flash Memory Data 2 PWR - 3.3 Volt Power GND - Ground I/O PU – 70k Flash Memory Data 3 I/O PU – ...
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... GPIO Enable I PD -60k Test Mode Enable I PU -70k JTAG Test Mode Select I PU -70k JTAG Test Clock O - JTAG Test Data Out I PU -70k JTAG Test Data -70k JTAG Test Reset 11 SiI3114 PCI to Serial ATA Controller Data Sheet SiI-DS-0103-D ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet Pin Type I-Schmitt Note: PCI pins are 5V tolerant. SiI-DS-0103-D Table 10. Pin Types Description I Input Pin with LVTTL Thresholds Input Pin with Schmitt Trigger O Output Pin T Tri-state Output Pin I/O Bi-directional Pin OD Open Drain Output Pin 12 Silicon Image, Inc ...
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... Silicon Image, Inc. SiI3114 Pin Diagram Figure 3 shows the SiI3114 pinout. Note that most PCI signals are not labeled with the “PCI_” prefix as used elsewhere. VSSO 133 STOP_N 134 DEVSEL_N 135 TRDY_N 136 SERR_N 137 VDDI 138 VSSI 139 PAR ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet SiI3114 Pin Descriptions PCI 66MHz 32-bit PCI Address and Data Pin Names: PCI_AD[31..00] Pin Numbers: 104-109, 112, 113, 116-118, 123-127, 142, 143, 146, 147, 150, 151, 153, 154, 160-167 Address and Data buses are multiplexed on the same PCI pins. A bus transaction consists of an address phase followed by one or more data phases ...
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... Clock Signal provides timing for all transactions on PCI and is an input to every PCI device. All other PCI signals (except PCI_RST_N, and PCI_INTA_N) are sampled on the rising edge of PCI_CLK. All other timing parameters are defined with respect to this edge. © 2007 Silicon Image, Inc. SiI3114 PCI to Serial ATA Controller 15 Data Sheet SiI-DS-0103-D ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet PCI Reset Pin Name: PCI_RST_N Pin Number: 96 PCI_RST_N is an active low input that is used to set the internal registers to their initial state. PCI_RST_N is typically the system power-on reset signal as distributed on the PCI bus. PCI M66EN ...
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... Pin Number: 25 PLL 1.8 V Power supply Pin Pin Name: VDDX Pin Number: 20 Oscillator 1.8 V Power supply Pin Pin Name: GNDA Pin Numbers 11, 14, 16, 23, 26, 29, 31, 35, 38, 40 SerDes Ground © 2007 Silicon Image, Inc. SiI3114 PCI to Serial ATA Controller 17 Data Sheet SiI-DS-0103-D ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet High Speed Serial Signals Pin Names: RxN[0..3] Pin Numbers: 8, 17, 32, 41 Differential receive negative side. Pin Names: RxP[0..3] Pin Numbers: 9, 18, 33, 42 Differential receive positive side. Pin Names: TxN[0..3] Pin Numbers: 4, 13, 28, 37 Differential transmit negative side Pin Names: TxP[0 ...
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... SiI3114CT176 (176 pin TQFP standard package) SiI3114CTU (176 pin TQFP universal package) © 2007 Silicon Image, Inc. 22.0 SQ NOM 20.0 SQ NOM 0.18 NOM 0.40 NOM Dimensions in millimeters Figure 4. Package Drawing – 176 TQFP 19 SiI3114 PCI to Serial ATA Controller Data Sheet 133 132 89 88 1.00 NOM 0.10 NOM SiI-DS-0103-D ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet Package Markings Figure 5. Marking Specification – SiI3114CT176 Figure 6. Marking Specification – SiI3114CTU SiI-DS-0103-D 20 Silicon Image, Inc. © 2007 Silicon Image, Inc. ...
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... Silicon Image, Inc. Block Diagram The SiI3114 contains the major logic modules shown in Figure 7. PCI Interface © 2007 Silicon Image, Inc. Bus Data Interface FIFO PCI DMA Engine PCI DMA Engine Bus Data Interface FIFO Bus Data Interface FIFO PCI DMA ...
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... PCI Configuration Space registers. H Note: If both flash and EEPROM are installed, the PCI Configuration Space registers will be loaded with the EEPROM’s data. While the sequence is active, the SiI3114 responds to all PCI bus accesses with a Target Retry. FL_ADDR MEM_ADDR FL_DATA ...
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... Control byte = 1010 (Control Code) + 000 (Chip Select (Write Address) 3. Acknowledge 4. Starting address field = 00000000. 5. Acknowledge 6. Sequential data bytes separated by Acknowledges. 7. STOP condition. While the sequence is active, the SiI3114 responds to all PCI bus accesses with a Target Retry. SDAT t 1 SCLK FL_CS_N Figure 9 ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet Address Data Byte 00 D00 H 01 D01 H 02 D02 H 03 D03 H 04 D04 H 05 D05 H 06 D06 H 07 D07 H 08 D08 H 09 D09 H 0A D10 H 0B D11 H 0C D12 H 0D D13 H 0E D14 H 0F D15 ...
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... This section describes the registers within the SiI3114. PCI Configuration Space The PCI Configuration Space registers define he operation of the SiI3114 on the PCI bus. These registers are accessible only when the SiI3114 detects a Configuration Read or Write operation, with its IDSEL asserted, on the 32-bit PCI bus. Table 16 outlines the PCI Configuration space for the SiI3114. ...
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... Device ID This register defines the Device ID and Vendor ID associated with the SiI3114. The register bits are defined below. • Bit [31:16] : Device ID (R/W) – Device ID. This value in this bit field is determined by any one of three options: 1) This field defaults to 0x3114 to identify the device as a Silicon Image SiI3114 ...
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... Bit [21 MHz Capable (R) – 66 MHz PCI Operation Capable. This bit is hardwired indicate that the SiI3114 is 66 MHz capable. • Bit [20] : Capabilities List (R) – PCI Capabilities List. This bit is hardwired indicate that the SiI3114 has a PCI Power Management Capabilities register linked at offset 34 • ...
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... Bit [01] : Memory Space (R/W) – Memory Space Enable. This bit set enables the SiI3114 to respond to PCI memory space access. • Bit [00 Space (R/W) – IO Space Enable. This bit set enables the SiI3114 to respond to PCI IO space access. PCI Class Code – Revision ID ...
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... Reset Value: 0x0000_0001 This register defines the addressing of various control functions within the SiI3114. The register bits are defined below. • Bit [31:03] : Base Address Register 2 (R/W). This register defines the I/O Space base address for Channel 1 task file registers. • ...
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... This register defines the addressing of various control functions within the SiI3114. This register is enabled when input BA5_EN is set to one. See description for pin FL_ADDR[01]/BA5_EN in “Miscellaneous I/O” section on page 16 for more information. The register bits are defined below. • ...
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... Bit [00] : Exp ROM Enable (R/W) – Expansion ROM Enable. This bit is set to enable the Expansion ROM access. © 2007 Silicon Image, Inc. SiI3114 PCI to Serial ATA Controller Subsystem Vendor set the two bytes are system set the two bytes are system ...
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... Bit [15:08] : Interrupt Pin (R) – Interrupt Pin Used. This bit field is hardwired to 01 SiI3114 uses the INTA# interrupt. • Bit [07:00] : Interrupt Line (R/W) – Interrupt Line. This bit field is used by the system to indicate interrupt line routing information. The SiI3114 does not use this information. Configuration Address Offset: 40 ...
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... SiI3114 requires special initialization • Bit [20] : Reserved (R). This bit is reserved and returns zero on a read. • Bit [19] : PME Clock (R) – Power Management Event Clock. This bit is hardwired to 0. The SiI3114 does not support PME. • Bit [18:16] : PPM Rev (R) – PCI Power Management Revision. This bit field is hardwired to 010 compliance with the PCI Power Management Interface Specification revision 1.1. • ...
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... PPM Data bits (although current implementation hardwires the PPM Data to indicate 1 Watt). • Bit [08] : PME Ena (R) – PME Enable. This bit is hardwired to 0. The SiI3114 does not support PME. • Bit [07:02] : Reserved (R). This bit field is reserved and returns zeros on a read. ...
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... Reset Value: 0x0000_0000 This register defines the PRD Table Address register for Channel 1/3 in the SiI3114. The register bits are also mapped to Base Address 4, Offset 0C section on page 54 for bit definitions. ...
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... Reset Value: 0x0000_0022 This register defines the transfer mode register for Channel 1/3 in the SiI3114. The register bits are also mapped to Base Address 5, Offset F4 . See “Data Transfer Mode – Channel X ” section on page 66 for bit definitions. ...
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... Reset Value: 0x0000_0000 This register defines the data register for flash memory interface in the SiI3114. The register bits are also mapped to Base Address 5, Offset 54 . See “Flash Memory Data” section on page 59 for bit definitions. ...
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... Reserved This register defines the task file configuration and status register for Channel 0/2 in the SiI3114. The register bits are also mapped to Base Address 5, Offset A0 page 65 for bit definitions. ...
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... Reserved This register defines the task file configuration and status register for Channel 1/3 in the SiI3114. The register bits are also mapped to Base Address 5, Offset E0 page 65 for bit definitions. ...
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... Starting Sector Number This register defines four of the Channel 0/2 Task File registers in the SiI3114. The register bits are also mapped to Base Address 5, Offset 80 . See “Channel X Task File Register 0” section on page 62 for bit definitions. The H value in the “ ...
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... Reserved This register defines one of the Channel 0/2 Task File registers in the SiI3114. The register bits are also mapped to Base Address 5, Offset 88 . See “Channel X Task File Register 2” section on page 63 for bit definitions. The H value in the “ ...
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... Starting Sector Number This register defines four of the Channel 1/3 Task File registers in the SiI3114. The register bits are also mapped to Base Address 5, Offset C0 . See “Channel X Task File Register 0” section on page 62 for bit definitions. The H value in the “ ...
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... Reserved This register defines one of the Channel 1/3 Task File registers in the SiI3114. The register bits are also mapped to Base Address 5, Offset C8 . See “Channel X Task File Register 2” section on page 63 for bit definitions. The H value in the “ ...
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... Reserved This register defines the PCI bus master register for Channel 0/2 in the SiI3114. See “PCI Bus Master – Channel X ” section on page 53 for bit definitions. The value in the “shadow” Channel 0/2 Device Select bit is used to control access to the appropriate Channel 0 (Master ...
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... Reserved This register defines the PCI bus master register for Channel 1/3 in the SiI3114. See “PRD Table Address – Channel X ” section on page 54 for bit definitions. The value in the “shadow” Channel 1/3 Device Select bit is used to control access to the appropriate Channel 1 (Master ...
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... Data Sheet Internal Register Space – Base Address 5 These registers are 32-bits wide and define the internal operation of the SiI3114. The access types are defined as follows: R=read, W=write, and C=clearable by some write operation. Access to this register is through the PCI Memory space. Base Address 5 accesses can be disabled by setting input BA5_EN low. Table 22 shows the internal register space for base 5 addresses. Table 22. SiI3114 Internal Register Space – ...
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... Device Control Auxiliary Status Channel 1 Read Ahead Data Channel 1 TF Channel 1 TF Sector Features2 Channel 1 Count2 TF Error2 Channel 1 TF Channel 1 TF Device+Head2 Cylinder High2 47 SiI3114 PCI to Serial ATA Controller Data Sheet Access Type 00 FIFO Byte2 Read R Pointer – Channel 0 R/W - FIFO Byte0 Read R Pointer – ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet Address Offset 31 Channel Cylinder High 2 H Ext 100 H 104 H 108 H 10C H 110 H 114 H 118 H 11C H 120 H 124 H 128 H 12C H 130 H 134 H 138 H 13C H 140 ...
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... PCI Bus Master Status2 – Channel Reserved 3 Reserved PRD Address – Channel 2 PCI Bus Master Byte Count – Channel 2 PRD Address – Channel 3 PCI Bus Master Byte Count – Channel 3 Reserved 49 SiI3114 PCI to Serial ATA Controller Data Sheet Access Type 00 R ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet Address Offset 31 234 H 238 H 23C H 240 FIFO Valid Byte Count – Channel 2 H 244 FIFO Valid Byte Count – Channel 3 H 248 System Configuration Status H 24C H 250 - H 25C H 260 H 264 H FIFO Byte1 Write 268 Pointer – ...
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... SActive (channel 2) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SMisc (channel 2) Reserved SIEN (channel 2) 51 SiI3114 PCI to Serial ATA Controller Data Sheet Access Type 00 Channel 2 Data R/W Transfer Mode - - R/W Channel 3 TF Data Channel 3 TF R/W Cylinder Low R/W Reserved ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet Address Offset 31 34C H 350 H 354 H 358 H 35C H 360 H 364 H 368 H 36C H 370 H 374 H 378 H 37C H 380 H 384 H 388 H 38C H 390 H 394 H 398 H 39C H 3A0 H 3A4 H 3A8 H 3AC H 3B0 H 3B4 H 3B8 H 3BC H 3C0 H 3C4 H 3C8 ...
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... SiI3114 was bus master. Additional information is available in the PCI Status register in PCI Configuration space. • Bit [16] : PBM Active (R) – PCI Bus Master Active – Channel X . This bit set indicates that the SiI3114 is currently active in a data transfer as PCI bus master. This bit is cleared by the hardware when all data transfers have completed or PBM Enable bit is not set. • ...
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... Reserved for Chnl 1/3 This register defines the second PCI bus master register for Channel X in the SiI3114. The system must access these register bits through this address to enable the Large Block Transfer Mode. ...
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... SiI3114 was bus master. Additional information is available in the PCI Status register in PCI Configuration space. • Bit [16] : PBM Active (R) – PCI Bus Master Active – Channel 0. This bit set indicates that the SiI3114 i s currently active in a data transfer as PCI bus master. This bit is cleared by the hardware when all data transfers have completed or PBM Enable bit is not set. • ...
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... Byte Count High This register defines the byte count register in the PCI bus master logic for Channel X in the SiI3114. The register bits are defined below. ...
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... Reserved This register defines the FIFO valid byte count register and PCI bus request control for Channel X in the SiI3114. The register bits are defined below. ...
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... Reset Value: 0x0800_0000 Reserved This register defines the address and command/status register for flash memory interface in the SiI3114. The register bits are defined below. SiI-DS-0103-D ...
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... Reserved This register defines the data register for the Flash memory and GPIO interface in the SiI3114. The system writes to this register for a write operation to Flash memory, and reads from this register on a read operation from Flash memory ...
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... This register defines the direct access register for the FIFO port of Channel X in the SiI3114. This register is used for hardware debugging purposes only. The system can read from or write to this register for direct access to the data FIFO between the PCI bus and Channel X ...
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... FIFO Byte 1 Wr Pointer This register provides visibility into the data FIFO for Channel X in the SiI3114. The data FIFO is organized as a four byte-wide x 64 deep memory array. There are separate write and read pointers for each of the byte slices. ...
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... Command + Status This register defines one of the Channel X Task File registers in the SiI3114. Access to these bit fields is permitted if the PCI bus Byte Enables are active for one byte only. ...
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... This register defines the read ahead data port for PIO transfers on Channel X in the SiI3114. This register can be accessed as an 8-bit, 16-bit, or 32-bit word, depending upon the PCI bus Byte Enables. The data written to this register must be zero-aligned. © ...
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... This register defines one of the Channel X Task File registers used for Command Buffered accesses in the SiI3114. The register bits are defined below. The Channel 0 and Channel 1 Device Select bits (bit 4 of the byte, bit 20 of this register) MUST be 0 for proper operation of the Task File registers when accessed via Base Address 5 ...
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... This register defines the read ahead byte count register for Virtual DMA and PIO Read Ahead transfers on Channel X in the SiI3114. In Virtual DMA mode (PCI bus master DMA with PIO transfers), all 32 bits are used as the word-aligned byte count. In PIO Read Ahead mode, only the lower 16 bits are used as the word-aligned byte count ...
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... This register defines the transfer mode register for Channel 0 in the SiI3114. The register bits are defined below. • Bit [31:08] : Reserved (R). This bit field is reserved and returns zeros on a read. ...
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... Bit [03:00] : DET – This field controls host adapter device detection and interface initialization. Value Action 0000 No action 0001 ATA Reset is generated until another value is written to the field 0100 No action others Reserved, no action © 2007 Silicon Image, Inc. / 380 H PMP Reserved 67 SiI3114 PCI to Serial ATA Controller Data Sheet IPM SPD DET SiI-DS-0103-D ...
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... Device presence detected and PHY communication established 0100 PHY in offline mode as a result of the interface being disabled or running in a BIST loopback mode others Reserved, no action Until a device is detected (IPM and DET fields become nonzero), the SiI3114 issues a COMRESET every 100 milliseconds. SiI-DS-0103-D / 384 H Reserved 68 Silicon Image, Inc ...
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... Indicates a change in the status of the Serial ATA PHY Latched Handshake error from the Serial ATA PHY Always 0 N/A, always 0 N/A, always 0 Latched ComWake status from the Serial ATA PHY Table 26. SError Register Bits (ERR Field) 69 SiI3114 PCI to Serial ATA Controller Data Sheet ERR Description ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet Serial ATA SActive Address Offset: 10C / 18C / 30C H H Access Type: Read/Write 1/Clear Reset Value: 0x0000_0000 The bits of this register may be written with a 1, but are cleared if the corresponding bits of the second dword of a FIS are set when the SDevice Bits FIS is received. All 32 bits may be cleared by writing 0x0000_0000 to the register ...
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... Silicon Image, Inc. • Bit [20] : Cont_dis (R/W)– Setting this bit disables the CONT primitive, i.e., the SiI3114 will always send the actual primitive instead of a CONT followed by random data. • Bit [19] : VS_Lock_Abort (R/W)– This bit controls the changes to the entries in the Command Protocol Table upon receiving a VS_Lock command ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet • Bit[18:14] : Reserved. The values of these bits should not be changed from their defaults otherwise erratic operation may result • Bit[13] : Tx_Swing_0: This bit, together with Tx_Swing_1, sets the nominal output swing for the Transmitter. ...
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... These registers contain 7 dwords from a Serial ATA FIS reception. © 2007 Silicon Image, Inc. / 3CC H H –1F8 / 360 –378 / 3E0 –3F8 FIS Dword 73 SiI3114 PCI to Serial ATA Controller Data Sheet SiI-DS-0103-D ...
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... FIFO Valid Byte Count and Control Channel x register. The read threshold is defined by bits [05:00], and the write threshold is defined by bits [13:08] in the FIFO Valid Byte Count and Control – Channel x register. In most environments, setting these bit fields to zero results in the best utilization of the PCI bus by the SiI3114 controller. ...
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... Ultra DMA Mode 6 H • Programming bits [31:24] in the Channel x Task File Register 1 register with the value = EF • Wait for the command to complete (see above). © 2007 Silicon Image, Inc SiI3114 PCI to Serial ATA Controller Data Sheet H SiI-DS-0103-D ...
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... Once the SiI3114 is initialized via the initialization sequence described in the “Recommended Initialization Sequence for the SiI3114” section, the ATA device has been initialized for PIO mode data transfer per the guidelines in the “Serial ATA Device Initialization” section, and the controller channel has been initialized for PIO mode data transfer, PIO read/write operations may be performed by following the programming sequence described below ...
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... Register 0 register, until the expected number of sectors of data per interrupt are read. Repeat the read operation steps until all data for the read command has been transferred or an error has been detected. © 2007 Silicon Image, Inc. SiI3114 PCI to Serial ATA Controller 77 Data Sheet SiI-DS-0103-D ...
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... Once the SiI3114 is initialized via the initialization sequence described in the “Recommended Initialization Sequence for the SiI3114” section, and the SATA device has been initialized for MDMA/UDMA mode data transfer per the guidelines in the “Serial ATA Device Initialization” section, DMA read/write operations may be performed by following the programming sequence described below. Issue a DMA read/write command to the device following the steps in the “ ...
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... If the device does not report an error, then the PRD specified a size that is larger than the B transfer size. Make sure PCI bus master operation of the SiI3114 is stopped by clearing bit 0 of the PCI Bus Master – Channel x register. Note: The task file registers are not accessible as long as bit 0 is set. Clearing bit 0 causes bit cleared as well ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet Issue a PIO read/write command to the device following the steps in the “Issue ATA Command” section on page 76. Read Operation Wait for a PCI interrupt. Read the DMA status bits [18:16] of the PCI Bus Master – Channel x register, and check that bit 18 is set to make sure the interrupt was generated by the expected channel. If expected channel interrupted, read bits [11:10] of the channel’ ...
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... PIO type transfer mode before DMA operation is enabled, and must be re- programmed with the DMA/UDMA transfer type used during normal DMA operation once the virtual DMA operation is complete. © 2007 Silicon Image, Inc. SiI3114 PCI to Serial ATA Controller 81 Data Sheet SiI-DS-0103-D ...
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... Whenever DMA is initiated via the PCI Bus Master – Channel x registers, the foregoing limitations are enforced by the SiI3114 controller. A feature known as Large Block Transfer in the SiI3114 controller allows drivers to get around the 64k size and address limits of PRD table entries expected by existing drivers. Large Block Transfer simplifies the creation of PRD tables by reducing the number of table entries that need to be created and eliminating the need to make sure a memory region does not cross a 64k boundary ...
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... Silicon Image, Inc. Power Management Power Management in the SiI3114 is controlled by the register bits described in Table 28. Register Bits Description SMisc PMCHG This bit reports a change in the Power Management mode. It corresponds to the interrupt enabled by bit 26 of SIEN. Bit 6 SMisc PMMODE These bits report the power management mode status: bit 5 corresponds to Slumber mode; ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet If enabled, a PMACK will be sent to the device; if not enabled, a PMNAK will be sent. When the request is received and its acknowledgement is enabled, Slumber mode is entered. Slumber mode status is reported in both the SStatus register (‘0110’ in the IPM field) and the SMisc register (bit 5) ...
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... Supported as one group of unrecognized FIS, together with other unsupported FISes (FIS Code 27h, A6h, B8h, BFh, C7h, D4h, D9h) in the reception direction. All "Others" are controlled as a group via PCI registers - default to reject 85 SiI3114 PCI to Serial ATA Controller Data Sheet SiI-DS-0103-D ...
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... The host writes the data through the PCI interface. Note that the FIS header (Dword 0 that contains the FIS type) must also be written. The Transport/Link logic sends the FIS to the device. Note that: • There is no size limit on a transparent FIS. Data written to the SiI3114 from setting of Transmit_FIS to setting of FIS_Done (see below) will be transmitted in a FIS. • ...
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... Default to reject FIS without interlock. FISc7cfg[1:0] 01b Default to reject FIS without interlock. FISd4cfg[1:0] 01b Default to reject FIS without interlock. FISd9cfg[1:0] 01b Default to reject FIS without interlock. FISocfg[1:0] 01b Default to reject FIS without interlock. 87 SiI3114 PCI to Serial ATA Controller Data Sheet SiI-DS-0103-D ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet • Upon reception of an interlocked FIS (FISxxcfg[1:0] = '10'), the Link/Transport Logic sets the IntrlckFIS bit in the Smisc register. The following describes the possible sequence of events: Sequence 1: The Link Logic will continue to receive data while its buffer is being filled up. ...
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... BIST Signals When SiI3114 enters the BIST operation, the “PHY offline” mode will be set in the DET bits of the Sstatus register. This conditoin will remain asserted until the host generates an ATA reset (hreset_b asserted COMINIT is received from the device. ...
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... Data Sheet ATA Command Decoding Data Modes The SiI3114 PCI to Serial ATA Controller has an internal ATA interface. The data modes (Register mode, PIO mode and DMA mode) are of no significance. ATA Commands The SiI3114 decodes ATA commands in hardware. The commands supported include ATA/ATAPI-5 and ATA/ATAPI-6 commands, including the 48-bit LBA extended commands ...
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... A2h - EFh - F9h/00h - 37h 48-bit LBA Command F9h/04h - F9h/02h - F9h/03h Obsolesced command supported. F9h/01h The SiI3114 intercepts the command to set up the number C6h of sectors for a DRQ block upon this command. E6h - B0h/D9h - B0h/D8h - B0h/D2h - B0h/D4h - B0h/D1h Obsolesced command supported. B0h/D0h - ...
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... Read Long and Write Long commands are implemented in accordance with the ATA/ATAPI-3. The PIO Mode used (Mode significance in the SiI3114, as the ATA interface is internal. The number of vendor specific bytes is provided by the Serial ATA PIO Setup FIS from the downstream device as follows ((XC - 512 ÷ ...
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... Note: (The Number of Vendor Specific Bytes is "n" as determined by the Transfer Count in the PIO Setup FIS) Vendor Specific Command Support The SiI3114 supports most vendor specific commands that utilize existing protocols. Silicon Image's Vendor Specific Commands Silicon Image defines several vendor specific commands (all of which use Expanded Features in 48-bit LBA addressing) to support vendor specific and reserved commands: • ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet Vendor Specific, Reserved, Retired and Obsolesced Commands These types of commands are treated differently: • Vendor specific commands: Expect for those commands whose protocols are individually set (via the VS Unlock Individual and VS Set Command Protocol commands), the host or device must be unlocked via the VS Unlock Vendor Specific command before such commands can be issued ...
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... ATA device. Note that the lock will take effect in the Serial ATA host and the Serial ATA device even if an ABORT status is reported. © 2007 Silicon Image, Inc. SiI3114 PCI to Serial ATA Controller 95 Data Sheet ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet Bridge Device Vendor Specific Commands Feature Set/Command Summary Table 34. Vendor Specific Command Summary Command Command Code VS Lock B0h VS Unlock Vendor Specific B0h VS Unlock Reserved B0h VS Unlock Individual B0h VS Set General Protocol B0h VS Set Command Protocol ...
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... DEV B0h obs na obs DEV BSY DRDY SiI3114 PCI to Serial ATA Controller Data Sheet SiI-DS-0103-D ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet Feature Set Mandatory for all Serial ATA components supporting the VS feature set. Description This command locks the host and device bridges from supporting vendor specific commands. All vendor specific and reserved commands issued afterwards will be aborted. ...
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... DEV B0h obs na obs DEV BSY DRDY SiI3114 PCI to Serial ATA Controller Data Sheet SiI-DS-0103-D ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet Feature Set Mandatory for all Serial ATA components supporting the VS feature set. Description This command unlocks the host and device bridges to support vendor specific commands. Once this command is executed, the bridge(s) shall remain unlocked until: • ...
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... Silicon Image, Inc obs na obs DEV F0h obs na obs DEV BSY DRDY na na 101 SiI3114 PCI to Serial ATA Controller Data Sheet F1h 22h ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet Feature Set Optional for all Serial ATA components supporting the VS feature set. Description This command unlocks the host and device bridges to support reserved commands. Once this command is executed, the bridge(s) shall remain unlocked until: • ...
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... DEV F0h obs na obs DEV BSY DRDY na na 103 SiI3114 PCI to Serial ATA Controller Data Sheet SiI-DS-0103-D ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet Feature Set Optional for all Serial ATA components supporting the VS feature set. Description This command unlocks the host and device bridges to support individual vendor specific and reserved commands. Once this command is executed, the bridge(s) shall remain unlocked until: • ...
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... DEV1 B0h obs na obs DEV BSY DRDY na na 105 SiI3114 PCI to Serial ATA Controller Data Sheet SiI-DS-0103-D ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet Feature Set Mandatory for all Serial ATA components supporting the VS feature set. Description If the VS state is unlocked for vendor specific or for reserved, this command will set the General Protocol Code for the next vendor specific/reserved command(s), except for those individually set via the VS Set Command Protocol commands. The protocol shall be, or return to, Abort (Protocol Code = 00h) upon a lock event, i.e.: • ...
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... DEV B0h obs na obs DEV BSY DRDY na na 107 SiI3114 PCI to Serial ATA Controller Data Sheet Code Tag SiI-DS-0103-D ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet Feature Set Optional for all Serial ATA components supporting the VS feature set. Description If the VS state is unlocked for individual vendor specific/reserved commands, this command will set the protocol for the specific commands individual vendor specific/reserved commands are supported via a Command Protocol Table ...
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... In other words, regardless of the status reported (aborted or complete), the Serial ATA host and device that support this scheme shall accept the protocol as valid. State Transitions Table 37 through Table 44 describe the state transitions of the SiI3114. VS_LOCKED 1 Received VS Unlock Vendor Specific command ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet VS_RSV 1 Received VS Unlock Vendor Specific command 2 Received VS Unlock Individual command 3 Received VS Lock command 4 Otherwise VS_IND 1 Received VS Unlock Reserved command 2 Received VS Unlock Individual command 3 Received VS Lock command 4 Otherwise VS_VS_RSV 1 Received VS Unlock Individual command 2 Received VS Lock command ...
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... All vendor specific/reserved commands with entries in the Command Protocol Table shall be executed according to the Protocol Code in the corresponding Command Protocol entry. All other vendor specific/reserved commands shall be executed according to the General Protocol Code. 111 SiI3114 PCI to Serial ATA Controller Data Sheet → VS_VS_RSV_IND → VS_LOCKED → ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet Protocols Summary The protocol encoding scheme is described in Table 45. Protocol Protocol Code 00h Abort 01h-3Fh A2h-AFh B3h-BFh - E0h-EFh F1h-FFh 40h-4Fh - 80h-8Fh C0h-CFh PIO Data in/Out (1x00xxxxb) 90h-9Fh D0h-DFh DMA (1x01xxxxb) A0h Packet A1h Service B0h,F0h ...
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... Write DMA protocol for 48-bit LBA commands. 99h Write DMA queued protocol. D9h Write DMA queued for 48-bit LBA commands. 8Fh PIO Data Out protocol, 512 plus vendor specific bytes, e.g. Write Long 113 SiI3114 PCI to Serial ATA Controller Data Sheet SiI-DS-0103-D ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet Table 47. Vendor Specific Protocol Code (by Protocol Code) Protocol Protocol Code 00h Abort 80h PIO Data In (Sectors) 81h PIO Data In (Single Sector) 82h PIO Data In (Read Multiple) 87h Read Long 88h PIO Data Out (Sectors) ...
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... Read DMA Queued Ext 87h Read Long A1h Service 98h Write DMA D8h Write DMA Ext, Write Stream DMA 99h Write DMA Queued D9h Write DMA Queued Ext 8Fh Write Long 115 SiI3114 PCI to Serial ATA Controller Data Sheet SiI-DS-0103-D ...
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... Wake up the downstream Serial ATA device from ATA IDLE, STANDBY or SLEEP. LED Support The SiI3114 supports four activity LEDs via four 12mA open-drain drivers LED[0..3]. LED0 is to indicate activity in channel 0; LED1 in channel 1; LED2 in channel 2; and LED3 in channel3. When there is activity for a non-ATAPI device, as indicated by: • ...
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... Silicon Image, Inc. Flash and EEPROM Programming Sequences Flash Memory Access The SiI3114 supports an external flash memory device Mbit in capacity. Access to the Flash memory is available through two means: PCI Direct Access and Register Access. PCI Direct Access Access to the Expansion Rom is enabled by setting bit 0 in the Expansion Rom Base Address register at Offset 30h of the PCI Configuration Space ...
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... SiI3114 PCI to Serial ATA Controller Data Sheet EEPROM Memory Access The SiI3114 supports an external 256-byte EEPROM memory device. Access to the EEPROM memory is available through internal register operations in the SiI3114. EEPROM Write Operation Verify that bit 25 is cleared in the EEPROM Memory Address – Command + Status register at Offset 58 of Base Address 5 ...
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... POTENTIAL HAZARD. NO PERSON IS AUTHORIZED TO MAKE ANY OTHER WARRANTY OR REPRESENTATION CONCERNING THE PERFORMANCE OF THE INFORMATION, PRODUCTS, KNOW- HOW, DESIGNS OR SERVICES OTHER THAN AS PROVIDED IN THESE TERMS AND CONDITIONS. © 2007 Silicon Image, Inc. SiI3114 PCI to Serial ATA Controller T 408.616.4000 F 408.830.9530 119 Data Sheet 1060 E ...