sii3114 Silicon image, sii3114 Datasheet - Page 85

• Manufacturer Part Number: sii3114
• Description: Pci To Serial Ata Controller
• Manufacturer: Silicon image

Silicon Image, Inc.
Watchdog Timer Operation
The purpose of the watchdog timer is to prevent the host system from hanging because a device operating in PIO
mode stopped responding to task file accesses. If, during a task file access by the host, the device negates
IORDY and then stops responding, the host will hang waiting for the access to complete. It is this type of hang,
that the watchdog timer is designed to protect against.
The watchdog timer monitors the length of time the IORDY signal is negated. If the watchdog timer detects that
the IORDY signal has remained negated longer than the watchdog timeout period (approximately 1000 PCI
clocks), the watchdog timer will force the task file access cycle to complete, and set the watchdog timeout bit in
the Channel x Task File Timing + Configuration + Status register. The data associated with a timed out access
should be considered invalid. Additionally, the watchdog timer can be configured to generate an interrupt when a
timeout is detected by setting bit 14 of the Channel x Task File Timing + Configuration + Status register.
The watchdog timer feature is disabled by default.
In addition to the controller channel initialization specified previously, add the following two steps to enable the
watchdog timer:
The following programming sequences are needed for each PIO Mode Read/Write Operation with the watchdog
timer enabled:
© 2007 Silicon Image, Inc.
• Enable the watchdog timer by setting bit 13 of the Channel x Task File Timing + Config + Status register.
• If an interrupt is desired whenever the watchdog times out, enable the watchdog interrupt by setting bit 14
of the Channel x Task File Timing + Config + Status register.
Read the device status at bits [31:24] in the Channel x Task File Register 1 register to clear the device
interrupt and determine if there was error.
If no error, repeat the previous four steps until all data for the write command has been transferred or an
error has been detected.
Issue a Read/Write PIO Command to the ATA drive following the steps in “Issue ATA Command” section
on page 76.
Read Operation
Wait for a channel interrupt.
If the ATA device interrupt bit is set,
Repeat the read operation steps until all data for the read command has been transferred or an error has
been detected.
If the watchdog timeout bit is set,
If controller interrupts are disabled, poll for the interrupt by reading the Channel x Task
File Timing + Configuration + Status register. If bit 12 is set, a watchdog timeout has
occurred. If bit 11 is set, the ATA device is interrupting.
Write 1 to bit 12 in the Channel x Task File Timing + Configuration + Status register to clear
watchdog timeout status.
The watchdog timeout represents a fatal error as far as the current ATA command is concerned.
A course of action that might be appropriate at this point might be to reset and reinitialize the ATA
channel and then retrying the command that failed.
Read the device status at bits [31:24] in the Channel x Task File Register 1 register to clear the
device interrupt and determine if there was an error.
Write 1 to bit 18 of the PCI Bus Master – Channel x Register to clear the ATA interrupt.
If the ATA device is not reporting an error, continue to read data via the Channel x Task File
Register 0 register, until the expected number of sectors of data per interrupt are read.
77
SiI3114 PCI to Serial ATA Controller
SiI-DS-0103-D
Data Sheet